From 19a004b46882f02ed5488f691abbbdc83bcc3ce4 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Wed, 21 Dec 2022 13:11:36 -0800 Subject: [PATCH] [llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets Follow up to the series: 1. https://reviews.llvm.org/D140161 2. https://reviews.llvm.org/D140349 3. https://reviews.llvm.org/D140331 4. https://reviews.llvm.org/D140323 Completes the work from the previous two for remaining targets. This creates the following named passes that can be run via `llc -{start|stop}-{before|after}`: - arc-isel - arm-isel - avr-isel - bpf-isel - csky-isel - hexagon-isel - lanai-isel - loongarch-isel - m68k-isel - msp430-isel - mips-isel - nvptx-isel - ppc-codegen - riscv-isel - sparc-isel - systemz-isel - ve-isel - wasm-isel - xcore-isel A nice way to write tests for SelectionDAGISel might be to use a RUN: line like: llc -mtriple= -start-before=-isel -stop-after=finalize-isel -o - Fixes: https://github.com/llvm/llvm-project/issues/59538 Reviewed By: asb, zixuan-wu Differential Revision: https://reviews.llvm.org/D140364 --- llvm/lib/Target/ARC/ARC.h | 4 +- llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp | 11 ++-- llvm/lib/Target/ARC/ARCTargetMachine.cpp | 2 + llvm/lib/Target/ARM/ARM.h | 25 ++++---- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 7 ++- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 1 + llvm/lib/Target/AVR/AVR.h | 4 +- llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp | 22 +++---- llvm/lib/Target/AVR/AVRTargetMachine.cpp | 1 + llvm/lib/Target/BPF/BPF.h | 16 ++--- llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 9 +-- llvm/lib/Target/BPF/BPFTargetMachine.cpp | 1 + llvm/lib/Target/CSKY/CSKY.h | 1 + llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp | 7 +-- llvm/lib/Target/CSKY/CSKYTargetMachine.cpp | 1 + llvm/lib/Target/Hexagon/Hexagon.h | 3 + llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 3 + llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h | 6 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 3 +- llvm/lib/Target/Lanai/Lanai.h | 3 + llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp | 10 ++-- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 2 + llvm/lib/Target/LoongArch/LoongArch.h | 8 +-- .../lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp | 3 + llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h | 6 +- .../Target/LoongArch/LoongArchTargetMachine.cpp | 1 + llvm/lib/Target/M68k/M68k.h | 3 + llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 10 ++-- llvm/lib/Target/M68k/M68kTargetMachine.cpp | 1 + llvm/lib/Target/MSP430/MSP430.h | 15 +++-- llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 9 +-- llvm/lib/Target/MSP430/MSP430TargetMachine.cpp | 2 + llvm/lib/Target/Mips/Mips.h | 69 +++++++++++----------- llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 3 + llvm/lib/Target/Mips/MipsISelDAGToDAG.h | 7 +-- llvm/lib/Target/Mips/MipsTargetMachine.cpp | 1 + llvm/lib/Target/NVPTX/NVPTX.h | 6 +- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 3 + llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 6 +- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 9 +-- llvm/lib/Target/PowerPC/PPC.h | 1 + llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 9 +-- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 1 + llvm/lib/Target/RISCV/RISCV.h | 9 +-- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 3 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 6 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 + llvm/lib/Target/Sparc/Sparc.h | 23 ++++---- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 11 ++-- llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 3 + llvm/lib/Target/SystemZ/SystemZ.h | 9 +-- llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 10 ++-- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp | 1 + llvm/lib/Target/VE/VE.h | 6 +- llvm/lib/Target/VE/VEISelDAGToDAG.cpp | 11 ++-- llvm/lib/Target/VE/VETargetMachine.cpp | 3 + llvm/lib/Target/WebAssembly/WebAssembly.h | 35 +++++------ .../Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 9 +-- .../WebAssembly/WebAssemblyTargetMachine.cpp | 1 + llvm/lib/Target/XCore/XCore.h | 2 + llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp | 11 ++-- llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 2 + 62 files changed, 277 insertions(+), 194 deletions(-) diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h index cbbf023..d8ccc47 100644 --- a/llvm/lib/Target/ARC/ARC.h +++ b/llvm/lib/Target/ARC/ARC.h @@ -19,14 +19,16 @@ namespace llvm { -class FunctionPass; class ARCTargetMachine; +class FunctionPass; +class PassRegistry; FunctionPass *createARCISelDag(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel); FunctionPass *createARCExpandPseudosPass(); FunctionPass *createARCOptAddrMode(); FunctionPass *createARCBranchFinalizePass(); +void initializeARCDAGToDAGISelPass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp index a0bf17d..80a38d0 100644 --- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp @@ -32,6 +32,9 @@ using namespace llvm; +#define DEBUG_TYPE "arc-isel" +#define PASS_NAME "ARC DAG->DAG Pattern Instruction Selection" + /// ARCDAGToDAGISel - ARC specific code to select ARC machine /// instructions for SelectionDAG operations. namespace { @@ -40,6 +43,8 @@ class ARCDAGToDAGISel : public SelectionDAGISel { public: static char ID; + ARCDAGToDAGISel() = delete; + ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel) {} @@ -51,16 +56,14 @@ public: bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset); bool SelectAddrModeFar(SDValue Addr, SDValue &Base, SDValue &Offset); - StringRef getPassName() const override { - return "ARC DAG->DAG Pattern Instruction Selection"; - } - // Include the pieces autogenerated from the target description. #include "ARCGenDAGISel.inc" }; char ARCDAGToDAGISel::ID; +INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + } // end anonymous namespace /// This pass converts a legalized DAG into a ARC-specific DAG, ready for diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index eba81b2..2527d6a 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -89,6 +89,8 @@ MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo( // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { RegisterTargetMachine X(getTheARCTarget()); + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeARCDAGToDAGISelPass(PR); } TargetTransformInfo diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h index 9990078..2013bfd 100644 --- a/llvm/lib/Target/ARM/ARM.h +++ b/llvm/lib/Target/ARM/ARM.h @@ -28,8 +28,8 @@ class ARMSubtarget; class Function; class FunctionPass; class InstructionSelector; -class MachineInstr; class MCInst; +class MachineInstr; class PassRegistry; Pass *createMVETailPredicationPass(); @@ -62,23 +62,24 @@ FunctionPass *createARMFixCortexA57AES1742098Pass(); void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP); -void initializeARMParallelDSPPass(PassRegistry &); -void initializeARMLoadStoreOptPass(PassRegistry &); -void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); +void initializeARMBlockPlacementPass(PassRegistry &); void initializeARMBranchTargetsPass(PassRegistry &); void initializeARMConstantIslandsPass(PassRegistry &); +void initializeARMDAGToDAGISelPass(PassRegistry &); void initializeARMExpandPseudoPass(PassRegistry &); -void initializeThumb2SizeReducePass(PassRegistry &); -void initializeThumb2ITBlockPass(PassRegistry &); -void initializeMVEVPTBlockPass(PassRegistry &); -void initializeMVETPAndVPTOptimisationsPass(PassRegistry &); +void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); +void initializeARMLoadStoreOptPass(PassRegistry &); void initializeARMLowOverheadLoopsPass(PassRegistry &); -void initializeARMBlockPlacementPass(PassRegistry &); -void initializeMVETailPredicationPass(PassRegistry &); -void initializeMVEGatherScatterLoweringPass(PassRegistry &); +void initializeARMParallelDSPPass(PassRegistry &); +void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); void initializeARMSLSHardeningPass(PassRegistry &); +void initializeMVEGatherScatterLoweringPass(PassRegistry &); void initializeMVELaneInterleavingPass(PassRegistry &); -void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); +void initializeMVETPAndVPTOptimisationsPass(PassRegistry &); +void initializeMVETailPredicationPass(PassRegistry &); +void initializeMVEVPTBlockPass(PassRegistry &); +void initializeThumb2ITBlockPass(PassRegistry &); +void initializeThumb2SizeReducePass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index e34d3e9..b3865e8 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -40,6 +40,7 @@ using namespace llvm; #define DEBUG_TYPE "arm-isel" +#define PASS_NAME "ARM Instruction Selection" static cl::opt DisableShifterOp("disable-shifter-op", cl::Hidden, @@ -60,6 +61,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel { public: static char ID; + ARMDAGToDAGISel() = delete; + explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, tm, OptLevel) {} @@ -70,8 +73,6 @@ public: return true; } - StringRef getPassName() const override { return "ARM Instruction Selection"; } - void PreprocessISelDAG() override; /// getI32Imm - Return a target constant of type i32 with the specified @@ -364,6 +365,8 @@ private: char ARMDAGToDAGISel::ID = 0; +INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 3a9bd0e..2d4fc63 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -109,6 +109,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { initializeARMSLSHardeningPass(Registry); initializeMVELaneInterleavingPass(Registry); initializeARMFixCortexA57AES1742098Pass(Registry); + initializeARMDAGToDAGISelPass(Registry); } static std::unique_ptr createTLOF(const Triple &TT) { diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h index d29dc5f..020c3d4 100644 --- a/llvm/lib/Target/AVR/AVR.h +++ b/llvm/lib/Target/AVR/AVR.h @@ -23,6 +23,7 @@ namespace llvm { class AVRTargetMachine; class FunctionPass; +class PassRegistry; Pass *createAVRShiftExpandPass(); FunctionPass *createAVRISelDag(AVRTargetMachine &TM, @@ -31,8 +32,9 @@ FunctionPass *createAVRExpandPseudoPass(); FunctionPass *createAVRFrameAnalyzerPass(); FunctionPass *createAVRBranchSelectionPass(); -void initializeAVRShiftExpandPass(PassRegistry &); +void initializeAVRDAGToDAGISelPass(PassRegistry &); void initializeAVRExpandPseudoPass(PassRegistry &); +void initializeAVRShiftExpandPass(PassRegistry &); /// Contains the AVR backend. namespace AVR { diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp index 6e10590..67b822a 100644 --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -20,21 +20,22 @@ #include "llvm/Support/raw_ostream.h" #define DEBUG_TYPE "avr-isel" +#define PASS_NAME "AVR DAG->DAG Instruction Selection" -namespace llvm { +using namespace llvm; + +namespace { /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form). class AVRDAGToDAGISel : public SelectionDAGISel { public: static char ID; + AVRDAGToDAGISel() = delete; + AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} - StringRef getPassName() const override { - return "AVR DAG->DAG Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override; bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp); @@ -58,8 +59,12 @@ private: const AVRSubtarget *Subtarget; }; +} // namespace + char AVRDAGToDAGISel::ID = 0; +INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); @@ -579,10 +584,7 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) { } } -FunctionPass *createAVRISelDag(AVRTargetMachine &TM, - CodeGenOpt::Level OptLevel) { +FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM, + CodeGenOpt::Level OptLevel) { return new AVRDAGToDAGISel(TM, OptLevel); } - -} // end of namespace llvm - diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index 06a2c7d..b87664e 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -96,6 +96,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() { auto &PR = *PassRegistry::getPassRegistry(); initializeAVRExpandPseudoPass(PR); initializeAVRShiftExpandPass(PR); + initializeAVRDAGToDAGISelPass(PR); } const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const { diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 3de761b..b48c122 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -12,11 +12,11 @@ #include "MCTargetDesc/BPFMCTargetDesc.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" -#include "llvm/PassRegistry.h" #include "llvm/Target/TargetMachine.h" namespace llvm { class BPFTargetMachine; +class PassRegistry; ModulePass *createBPFAdjustOpt(); ModulePass *createBPFCheckAndAdjustIR(); @@ -31,17 +31,17 @@ FunctionPass *createBPFMIPeepholeTruncElimPass(); FunctionPass *createBPFMIPreEmitPeepholePass(); FunctionPass *createBPFMIPreEmitCheckingPass(); +void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &); void initializeBPFAdjustOptPass(PassRegistry&); void initializeBPFCheckAndAdjustIRPass(PassRegistry&); - -void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &); -void initializeBPFPreserveDITypePass(PassRegistry&); -void initializeBPFIRPeepholePass(PassRegistry&); -void initializeBPFMISimplifyPatchablePass(PassRegistry&); +void initializeBPFDAGToDAGISelPass(PassRegistry &); +void initializeBPFIRPeepholePass(PassRegistry &); void initializeBPFMIPeepholePass(PassRegistry&); -void initializeBPFMIPeepholeTruncElimPass(PassRegistry&); -void initializeBPFMIPreEmitPeepholePass(PassRegistry&); +void initializeBPFMIPeepholeTruncElimPass(PassRegistry &); void initializeBPFMIPreEmitCheckingPass(PassRegistry&); +void initializeBPFMIPreEmitPeepholePass(PassRegistry &); +void initializeBPFMISimplifyPatchablePass(PassRegistry &); +void initializeBPFPreserveDITypePass(PassRegistry &); class BPFAbstractMemberAccessPass : public PassInfoMixin { diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index b0358be..e830eb2 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -34,6 +34,7 @@ using namespace llvm; #define DEBUG_TYPE "bpf-isel" +#define PASS_NAME "BPF DAG->DAG Pattern Instruction Selection" // Instruction Selector Implementation namespace { @@ -47,13 +48,11 @@ class BPFDAGToDAGISel : public SelectionDAGISel { public: static char ID; + BPFDAGToDAGISel() = delete; + explicit BPFDAGToDAGISel(BPFTargetMachine &TM) : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} - StringRef getPassName() const override { - return "BPF DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. Subtarget = &MF.getSubtarget(); @@ -100,6 +99,8 @@ private: char BPFDAGToDAGISel::ID = 0; +INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + // ComplexPattern used on BPF Load/Store instructions bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { // if Address is FI, get the TargetFrameIndex. diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index e0b48f1..320acdb 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -48,6 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() { initializeBPFCheckAndAdjustIRPass(PR); initializeBPFMIPeepholePass(PR); initializeBPFMIPeepholeTruncElimPass(PR); + initializeBPFDAGToDAGISelPass(PR); } // DataLayout: little or big endian diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h index da995ac..871a7d7 100644 --- a/llvm/lib/Target/CSKY/CSKY.h +++ b/llvm/lib/Target/CSKY/CSKY.h @@ -27,6 +27,7 @@ FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM, FunctionPass *createCSKYConstantIslandPass(); void initializeCSKYConstantIslandsPass(PassRegistry &); +void initializeCSKYDAGToDAGISelPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp index 031b160..09c2d51 100644 --- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp +++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp @@ -21,6 +21,7 @@ using namespace llvm; #define DEBUG_TYPE "csky-isel" +#define PASS_NAME "CSKY DAG->DAG Pattern Instruction Selection" namespace { class CSKYDAGToDAGISel : public SelectionDAGISel { @@ -32,10 +33,6 @@ public: explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel) {} - StringRef getPassName() const override { - return "CSKY DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. Subtarget = &MF.getSubtarget(); @@ -60,6 +57,8 @@ public: char CSKYDAGToDAGISel::ID = 0; +INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + void CSKYDAGToDAGISel::Select(SDNode *N) { // If we have a custom node, we have already selected if (N->isMachineOpcode()) { diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index be73b5e..966e301 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -29,6 +29,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() { PassRegistry *Registry = PassRegistry::getPassRegistry(); initializeCSKYConstantIslandsPass(*Registry); + initializeCSKYDAGToDAGISelPass(*Registry); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h index 98e5710..861f61a 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.h +++ b/llvm/lib/Target/Hexagon/Hexagon.h @@ -17,9 +17,12 @@ namespace llvm { class HexagonTargetMachine; class ImmutablePass; + class PassRegistry; /// Creates a Hexagon-specific Target Transformation Info pass. ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM); + + void initializeHexagonDAGToDAGISelPass(PassRegistry &); } // end namespace llvm; #endif diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 6cda21a..855c4ac 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -25,6 +25,7 @@ using namespace llvm; #define DEBUG_TYPE "hexagon-isel" +#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection" static cl::opt @@ -65,6 +66,8 @@ FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, char HexagonDAGToDAGISel::ID = 0; +INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { SDValue Chain = LD->getChain(); SDValue Base = LD->getBasePtr(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 1dd069b..061da2a 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -33,6 +33,8 @@ class HexagonDAGToDAGISel : public SelectionDAGISel { public: static char ID; + HexagonDAGToDAGISel() = delete; + explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr), @@ -71,10 +73,6 @@ public: inline bool SelectAnyImm2(SDValue &N, SDValue &R); inline bool SelectAnyImm3(SDValue &N, SDValue &R); - StringRef getPassName() const override { - return "Hexagon DAG->DAG Pattern Instruction Selection"; - } - // Generate a machine instruction node corresponding to the circ/brev // load intrinsic. MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index aed075d..b52e1c9 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -156,9 +156,9 @@ namespace llvm { void initializeHexagonPacketizerPass(PassRegistry&); void initializeHexagonRDFOptPass(PassRegistry&); void initializeHexagonSplitDoubleRegsPass(PassRegistry&); + void initializeHexagonVExtractPass(PassRegistry &); void initializeHexagonVectorCombineLegacyPass(PassRegistry&); void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); - void initializeHexagonVExtractPass(PassRegistry&); Pass *createHexagonLoopIdiomPass(); Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); @@ -219,6 +219,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { initializeHexagonVectorCombineLegacyPass(PR); initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR); initializeHexagonVExtractPass(PR); + initializeHexagonDAGToDAGISelPass(PR); } HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h index 2bd266b..0f87b17 100644 --- a/llvm/lib/Target/Lanai/Lanai.h +++ b/llvm/lib/Target/Lanai/Lanai.h @@ -19,6 +19,7 @@ namespace llvm { class FunctionPass; class LanaiTargetMachine; +class PassRegistry; // createLanaiISelDag - This pass converts a legalized DAG into a // Lanai-specific DAG, ready for instruction scheduling. @@ -36,6 +37,8 @@ FunctionPass *createLanaiMemAluCombinerPass(); // operations. FunctionPass *createLanaiSetflagAluCombinerPass(); +void initializeLanaiDAGToDAGISelPass(PassRegistry &); + } // namespace llvm #endif // LLVM_LIB_TARGET_LANAI_LANAI_H diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index 0327951..b1ecebe 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -34,6 +34,7 @@ using namespace llvm; #define DEBUG_TYPE "lanai-isel" +#define PASS_NAME "Lanai DAG->DAG Pattern Instruction Selection" //===----------------------------------------------------------------------===// // Instruction Selector Implementation @@ -49,6 +50,8 @@ class LanaiDAGToDAGISel : public SelectionDAGISel { public: static char ID; + LanaiDAGToDAGISel() = delete; + explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine) : SelectionDAGISel(ID, TargetMachine) {} @@ -56,11 +59,6 @@ public: return SelectionDAGISel::runOnMachineFunction(MF); } - // Pass Name - StringRef getPassName() const override { - return "Lanai DAG->DAG Pattern Instruction Selection"; - } - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode, std::vector &OutOps) override; @@ -102,6 +100,8 @@ bool canBeRepresentedAsSls(const ConstantSDNode &CN) { char LanaiDAGToDAGISel::ID = 0; +INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + // Helper functions for ComplexPattern used on LanaiInstrInfo // Used on Lanai Load/Store instructions. bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) { diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index d9e958b..80a6095 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -36,6 +36,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() { // Register the target. RegisterTargetMachine registered_target( getTheLanaiTarget()); + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeLanaiDAGToDAGISelPass(PR); } static std::string computeDataLayout() { diff --git a/llvm/lib/Target/LoongArch/LoongArch.h b/llvm/lib/Target/LoongArch/LoongArch.h index 3d0a3b9..05f4ac8 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.h +++ b/llvm/lib/Target/LoongArch/LoongArch.h @@ -18,9 +18,9 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class LoongArchTargetMachine; class AsmPrinter; class FunctionPass; +class LoongArchTargetMachine; class MCInst; class MCOperand; class MachineInstr; @@ -33,11 +33,11 @@ bool lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP); -FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM); FunctionPass *createLoongArchExpandAtomicPseudoPass(); -void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &); - +FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM); FunctionPass *createLoongArchPreRAExpandPseudoPass(); +void initializeLoongArchDAGToDAGISelPass(PassRegistry &); +void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &); void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp index 8dfaf6f..9fe7d94 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp @@ -19,9 +19,12 @@ using namespace llvm; #define DEBUG_TYPE "loongarch-isel" +#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection" char LoongArchDAGToDAGISel::ID; +INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + void LoongArchDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we have already selected. if (Node->isMachineOpcode()) { diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h index 3474813..230151b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h @@ -26,13 +26,11 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel { public: static char ID; + LoongArchDAGToDAGISel() = delete; + explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM) : SelectionDAGISel(ID, TM) {} - StringRef getPassName() const override { - return "LoongArch DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index af785ce..1f41088 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -30,6 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() { RegisterTargetMachine Y(getTheLoongArch64Target()); auto *PR = PassRegistry::getPassRegistry(); initializeLoongArchPreRAExpandPseudoPass(*PR); + initializeLoongArchDAGToDAGISelPass(*PR); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/M68k/M68k.h b/llvm/lib/Target/M68k/M68k.h index b6069d7..71c4cf8 100644 --- a/llvm/lib/Target/M68k/M68k.h +++ b/llvm/lib/Target/M68k/M68k.h @@ -22,6 +22,7 @@ class InstructionSelector; class M68kRegisterBankInfo; class M68kSubtarget; class M68kTargetMachine; +class PassRegistry; /// This pass converts a legalized DAG into a M68k-specific DAG, ready for /// instruction scheduling. @@ -52,6 +53,8 @@ InstructionSelector * createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &, const M68kRegisterBankInfo &); +void initializeM68kDAGToDAGISelPass(PassRegistry &); + } // namespace llvm #endif // LLVM_LIB_TARGET_M68K_M68K_H diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp index dd3a1a0..d464c13 100644 --- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp +++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp @@ -39,6 +39,7 @@ using namespace llvm; #define DEBUG_TYPE "m68k-isel" +#define PASS_NAME "M68k DAG->DAG Pattern Instruction Selection" namespace { @@ -175,13 +176,11 @@ class M68kDAGToDAGISel : public SelectionDAGISel { public: static char ID; + M68kDAGToDAGISel() = delete; + explicit M68kDAGToDAGISel(M68kTargetMachine &TM) : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} - StringRef getPassName() const override { - return "M68k DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override; bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; @@ -314,6 +313,9 @@ private: }; char M68kDAGToDAGISel::ID; + +INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + } // namespace bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index 97b6d6a..efbef2a 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -37,6 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() { RegisterTargetMachine X(getTheM68kTarget()); auto *PR = PassRegistry::getPassRegistry(); initializeGlobalISel(*PR); + initializeM68kDAGToDAGISelPass(*PR); } namespace { diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h index 34f0a37..75fa398 100644 --- a/llvm/lib/Target/MSP430/MSP430.h +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -34,14 +34,17 @@ namespace MSP430CC { } namespace llvm { - class MSP430TargetMachine; - class FunctionPass; +class FunctionPass; +class MSP430TargetMachine; +class PassRegistry; - FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, - CodeGenOpt::Level OptLevel); +FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, + CodeGenOpt::Level OptLevel); - FunctionPass *createMSP430BranchSelectionPass(); +FunctionPass *createMSP430BranchSelectionPass(); -} // end namespace llvm; +void initializeMSP430DAGToDAGISelPass(PassRegistry &); + +} // namespace llvm #endif diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 07661ab..88f072c 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -30,6 +30,7 @@ using namespace llvm; #define DEBUG_TYPE "msp430-isel" +#define PASS_NAME "MSP430 DAG->DAG Pattern Instruction Selection" namespace { struct MSP430ISelAddressMode { @@ -92,14 +93,12 @@ namespace { public: static char ID; + MSP430DAGToDAGISel() = delete; + MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel) {} private: - StringRef getPassName() const override { - return "MSP430 DAG->DAG Pattern Instruction Selection"; - } - bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); @@ -123,6 +122,8 @@ namespace { char MSP430DAGToDAGISel::ID; +INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + /// createMSP430ISelDag - This pass converts a legalized DAG into a /// MSP430-specific DAG, ready for instruction scheduling. /// diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index e89b89f..c5b654c 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -26,6 +26,8 @@ using namespace llvm; extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() { // Register the target. RegisterTargetMachine X(getTheMSP430Target()); + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeMSP430DAGToDAGISelPass(PR); } static Reloc::Model getEffectiveRelocModel(std::optional RM) { diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h index 12dc29b..f0cf039 100644 --- a/llvm/lib/Target/Mips/Mips.h +++ b/llvm/lib/Target/Mips/Mips.h @@ -18,39 +18,40 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { - class MipsTargetMachine; - class ModulePass; - class FunctionPass; - class MipsRegisterBankInfo; - class MipsSubtarget; - class MipsTargetMachine; - class InstructionSelector; - class PassRegistry; - - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); - FunctionPass *createMipsBranchExpansion(); - FunctionPass *createMipsConstantIslandPass(); - FunctionPass *createMicroMipsSizeReducePass(); - FunctionPass *createMipsExpandPseudoPass(); - FunctionPass *createMipsPreLegalizeCombiner(); - FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone); - FunctionPass *createMipsMulMulBugPass(); - - InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, - MipsSubtarget &, - MipsRegisterBankInfo &); - - void initializeMipsDelaySlotFillerPass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsPreLegalizerCombinerPass(PassRegistry&); - void initializeMipsPostLegalizerCombinerPass(PassRegistry &); - void initializeMipsMulMulBugFixPass(PassRegistry&); -} // end namespace llvm; +class FunctionPass; +class InstructionSelector; +class MipsRegisterBankInfo; +class MipsSubtarget; +class MipsTargetMachine; +class MipsTargetMachine; +class ModulePass; +class PassRegistry; + +ModulePass *createMipsOs16Pass(); +ModulePass *createMips16HardFloatPass(); + +FunctionPass *createMipsModuleISelDagPass(); +FunctionPass *createMipsOptimizePICCallPass(); +FunctionPass *createMipsDelaySlotFillerPass(); +FunctionPass *createMipsBranchExpansion(); +FunctionPass *createMipsConstantIslandPass(); +FunctionPass *createMicroMipsSizeReducePass(); +FunctionPass *createMipsExpandPseudoPass(); +FunctionPass *createMipsPreLegalizeCombiner(); +FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone); +FunctionPass *createMipsMulMulBugPass(); + +InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, + MipsSubtarget &, + MipsRegisterBankInfo &); + +void initializeMicroMipsSizeReducePass(PassRegistry &); +void initializeMipsBranchExpansionPass(PassRegistry &); +void initializeMipsDAGToDAGISelPass(PassRegistry &); +void initializeMipsDelaySlotFillerPass(PassRegistry &); +void initializeMipsMulMulBugFixPass(PassRegistry &); +void initializeMipsPostLegalizerCombinerPass(PassRegistry &); +void initializeMipsPreLegalizerCombinerPass(PassRegistry &); +} // namespace llvm #endif diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 5d0383f..7266dfb 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -36,6 +36,7 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" +#define PASS_NAME "MIPS DAG->DAG Pattern Instruction Selection" //===----------------------------------------------------------------------===// // Instruction Selector Implementation @@ -324,3 +325,5 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, } char MipsDAGToDAGISel::ID = 0; + +INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h index e607dbe..d13efda 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -32,14 +32,11 @@ class MipsDAGToDAGISel : public SelectionDAGISel { public: static char ID; + MipsDAGToDAGISel() = delete; + explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {} - // Pass Name - StringRef getPassName() const override { - return "MIPS DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override; void getAnalysisUsage(AnalysisUsage &AU) const override; diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index e5e8333..fe31ab9 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -67,6 +67,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { initializeMipsPreLegalizerCombinerPass(*PR); initializeMipsPostLegalizerCombinerPass(*PR); initializeMipsMulMulBugFixPass(*PR); + initializeMipsDAGToDAGISelPass(*PR); } static std::string computeDataLayout(const Triple &TT, StringRef CPU, diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h index 8c92766..3bd9a7f 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.h +++ b/llvm/lib/Target/NVPTX/NVPTX.h @@ -19,9 +19,10 @@ #include "llvm/Support/CodeGen.h" namespace llvm { -class NVPTXTargetMachine; class FunctionPass; class MachineFunctionPass; +class NVPTXTargetMachine; +class PassRegistry; namespace NVPTXCC { enum CondCodes { @@ -174,7 +175,8 @@ enum CmpMode { }; } } -} // end namespace llvm; +void initializeNVPTXDAGToDAGISelPass(PassRegistry &); +} // namespace llvm // Defines symbolic names for NVPTX registers. This defines a mapping from // register name to register number. diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 1f706ab..a0358ce 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -27,6 +27,7 @@ using namespace llvm; #define DEBUG_TYPE "nvptx-isel" +#define PASS_NAME "NVPTX DAG->DAG Pattern Instruction Selection" /// createNVPTXISelDag - This pass converts a legalized DAG into a /// NVPTX-specific DAG, ready for instruction scheduling. @@ -37,6 +38,8 @@ FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM, char NVPTXDAGToDAGISel::ID = 0; +INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, tm, OptLevel), TM(tm) { diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h index 72f1bb2..746a9de 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -40,13 +40,11 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { public: static char ID; + NVPTXDAGToDAGISel() = delete; + explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOpt::Level OptLevel); - // Pass Name - StringRef getPassName() const override { - return "NVPTX DAG->DAG Pattern Instruction Selection"; - } bool runOnMachineFunction(MachineFunction &MF) override; const NVPTXSubtarget *Subtarget = nullptr; diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index dc207b0..4ef989c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -64,16 +64,16 @@ static cl::opt UseShortPointersOpt( namespace llvm { -void initializeNVVMIntrRangePass(PassRegistry&); -void initializeNVVMReflectPass(PassRegistry&); void initializeGenericToNVVMPass(PassRegistry&); void initializeNVPTXAllocaHoistingPass(PassRegistry &); -void initializeNVPTXAtomicLowerPass(PassRegistry &); void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&); +void initializeNVPTXAtomicLowerPass(PassRegistry &); void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); -void initializeNVPTXLowerArgsPass(PassRegistry &); void initializeNVPTXLowerAllocaPass(PassRegistry &); +void initializeNVPTXLowerArgsPass(PassRegistry &); void initializeNVPTXProxyRegErasurePass(PassRegistry &); +void initializeNVVMIntrRangePass(PassRegistry &); +void initializeNVVMReflectPass(PassRegistry &); } // end namespace llvm @@ -95,6 +95,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { initializeNVPTXLowerAllocaPass(PR); initializeNVPTXLowerAggrCopiesPass(PR); initializeNVPTXProxyRegErasurePass(PR); + initializeNVPTXDAGToDAGISelPass(PR); } static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) { diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 4eceb3a..8f84ae7 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -77,6 +77,7 @@ class ModulePass; void initializePPCMIPeepholePass(PassRegistry&); void initializePPCExpandAtomicPseudoPass(PassRegistry &); void initializePPCCTRLoopsPass(PassRegistry &); + void initializePPCDAGToDAGISelPass(PassRegistry &); extern char &PPCVSXFMAMutateID; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 5a7367b..176b49a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -69,6 +69,7 @@ using namespace llvm; #define DEBUG_TYPE "ppc-codegen" +#define PASS_NAME "PowerPC DAG->DAG Pattern Instruction Selection" STATISTIC(NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence."); @@ -147,6 +148,8 @@ namespace { public: static char ID; + PPCDAGToDAGISel() = delete; + explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {} @@ -412,10 +415,6 @@ namespace { return true; } - StringRef getPassName() const override { - return "PowerPC DAG->DAG Pattern Instruction Selection"; - } - // Include the pieces autogenerated from the target description. #include "PPCGenDAGISel.inc" @@ -449,6 +448,8 @@ private: char PPCDAGToDAGISel::ID = 0; +INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 3f51018..0a020b9 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -136,6 +136,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { initializePPCExpandAtomicPseudoPass(PR); initializeGlobalISel(PR); initializePPCCTRLoopsPass(PR); + initializePPCDAGToDAGISelPass(PR); } static bool isLittleEndianTriple(const Triple &T) { diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index 6b4493e..fbfbb8b 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -18,9 +18,6 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class RISCVRegisterBankInfo; -class RISCVSubtarget; -class RISCVTargetMachine; class AsmPrinter; class FunctionPass; class InstructionSelector; @@ -29,6 +26,9 @@ class MCOperand; class MachineInstr; class MachineOperand; class PassRegistry; +class RISCVRegisterBankInfo; +class RISCVSubtarget; +class RISCVTargetMachine; FunctionPass *createRISCVCodeGenPreparePass(); void initializeRISCVCodeGenPreparePass(PassRegistry &); @@ -71,6 +71,7 @@ void initializeRISCVRedundantCopyEliminationPass(PassRegistry &); InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &); -} +void initializeRISCVDAGToDAGISelPass(PassRegistry &); +} // namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 2a73b1e..2fb348e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -27,6 +27,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-isel" +#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection" namespace llvm::RISCV { #define GET_RISCVVSSEGTable_IMPL @@ -2909,3 +2910,5 @@ FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM, } char RISCVDAGToDAGISel::ID = 0; + +INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index f5ef5c5..350e90a 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -26,14 +26,12 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { public: static char ID; + RISCVDAGToDAGISel() = delete; + explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TargetMachine, OptLevel) {} - StringRef getPassName() const override { - return "RISCV DAG->DAG Pattern Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); return SelectionDAGISel::runOnMachineFunction(MF); diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index e84318c..fe9b2c4 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -80,6 +80,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVPreRAExpandPseudoPass(*PR); initializeRISCVExpandPseudoPass(*PR); initializeRISCVInsertVSETVLIPass(*PR); + initializeRISCVDAGToDAGISelPass(*PR); } static StringRef computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h index 4caae78..fca7657 100644 --- a/llvm/lib/Target/Sparc/Sparc.h +++ b/llvm/lib/Target/Sparc/Sparc.h @@ -19,19 +19,20 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { - class FunctionPass; - class SparcTargetMachine; - class AsmPrinter; - class MCInst; - class MachineInstr; +class AsmPrinter; +class FunctionPass; +class MCInst; +class MachineInstr; +class PassRegistry; +class SparcTargetMachine; - FunctionPass *createSparcISelDag(SparcTargetMachine &TM); - FunctionPass *createSparcDelaySlotFillerPass(); +FunctionPass *createSparcISelDag(SparcTargetMachine &TM); +FunctionPass *createSparcDelaySlotFillerPass(); - void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, - MCInst &OutMI, - AsmPrinter &AP); -} // end namespace llvm; +void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, + AsmPrinter &AP); +void initializeSparcDAGToDAGISelPass(PassRegistry &); +} // namespace llvm namespace llvm { // Enums corresponding to Sparc condition codes, both icc's and fcc's. These diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index af481e7..8339f5c 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -19,6 +19,9 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +#define DEBUG_TYPE "sparc-isel" +#define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection" + //===----------------------------------------------------------------------===// // Instruction Selector Implementation //===----------------------------------------------------------------------===// @@ -35,6 +38,8 @@ class SparcDAGToDAGISel : public SelectionDAGISel { public: static char ID; + SparcDAGToDAGISel() = delete; + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -54,10 +59,6 @@ public: unsigned ConstraintID, std::vector &OutOps) override; - StringRef getPassName() const override { - return "SPARC DAG->DAG Pattern Instruction Selection"; - } - // Include the pieces autogenerated from the target description. #include "SparcGenDAGISel.inc" @@ -69,6 +70,8 @@ private: char SparcDAGToDAGISel::ID = 0; +INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); return CurDAG->getRegister(GlobalBaseReg, diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 30570e8..58faaaf 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -27,6 +27,9 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { RegisterTargetMachine X(getTheSparcTarget()); RegisterTargetMachine Y(getTheSparcV9Target()); RegisterTargetMachine Z(getTheSparcelTarget()); + + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeSparcDAGToDAGISelPass(PR); } static std::string computeDataLayout(const Triple &T, bool is64Bit) { diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h index 5be19f0..cdd2850 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.h +++ b/llvm/lib/Target/SystemZ/SystemZ.h @@ -18,9 +18,9 @@ #include "llvm/Support/CodeGen.h" namespace llvm { -class SystemZTargetMachine; class FunctionPass; class PassRegistry; +class SystemZTargetMachine; namespace SystemZ { // Condition-code mask values. @@ -198,12 +198,13 @@ FunctionPass *createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM); FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM); FunctionPass *createSystemZTDCPass(); +void initializeSystemZCopyPhysRegsPass(PassRegistry &); +void initializeSystemZDAGToDAGISelPass(PassRegistry &); void initializeSystemZElimComparePass(PassRegistry &); -void initializeSystemZShortenInstPass(PassRegistry &); -void initializeSystemZLongBranchPass(PassRegistry &); void initializeSystemZLDCleanupPass(PassRegistry &); -void initializeSystemZCopyPhysRegsPass(PassRegistry &); +void initializeSystemZLongBranchPass(PassRegistry &); void initializeSystemZPostRewritePass(PassRegistry &); +void initializeSystemZShortenInstPass(PassRegistry &); void initializeSystemZTDCPassPass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 92d549f..59d4639 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -21,6 +21,7 @@ using namespace llvm; #define DEBUG_TYPE "systemz-isel" +#define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection" namespace { // Used to build addressing modes. @@ -347,6 +348,8 @@ class SystemZDAGToDAGISel : public SelectionDAGISel { public: static char ID; + SystemZDAGToDAGISel() = delete; + SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel) {} @@ -363,11 +366,6 @@ public: return SelectionDAGISel::runOnMachineFunction(MF); } - // Override MachineFunctionPass. - StringRef getPassName() const override { - return "SystemZ DAG->DAG Pattern Instruction Selection"; - } - // Override SelectionDAGISel. void Select(SDNode *Node) override; bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, @@ -382,6 +380,8 @@ public: char SystemZDAGToDAGISel::ID = 0; +INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) { return new SystemZDAGToDAGISel(TM, OptLevel); diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index d5f8659..787c516 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -41,6 +41,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { initializeSystemZShortenInstPass(PR); initializeSystemZPostRewritePass(PR); initializeSystemZTDCPassPass(PR); + initializeSystemZDAGToDAGISelPass(PR); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h index 4f7ec91..ded0460 100644 --- a/llvm/lib/Target/VE/VE.h +++ b/llvm/lib/Target/VE/VE.h @@ -22,14 +22,16 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class FunctionPass; -class VETargetMachine; class AsmPrinter; +class FunctionPass; class MCInst; class MachineInstr; +class PassRegistry; +class VETargetMachine; FunctionPass *createVEISelDag(VETargetMachine &TM); FunctionPass *createLVLGenPass(); +void initializeVEDAGToDAGISelPass(PassRegistry &); void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp index c7f4fcf..859c33df 100644 --- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp +++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp @@ -20,6 +20,9 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +#define DEBUG_TYPE "ve-isel" +#define PASS_NAME "VE DAG->DAG Pattern Instruction Selection" + //===--------------------------------------------------------------------===// /// VEDAGToDAGISel - VE specific code to select VE machine /// instructions for SelectionDAG operations. @@ -33,6 +36,8 @@ class VEDAGToDAGISel : public SelectionDAGISel { public: static char ID; + VEDAGToDAGISel() = delete; + explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -56,10 +61,6 @@ public: unsigned ConstraintID, std::vector &OutOps) override; - StringRef getPassName() const override { - return "VE DAG->DAG Pattern Instruction Selection"; - } - // Include the pieces autogenerated from the target description. #include "VEGenDAGISel.inc" @@ -73,6 +74,8 @@ private: char VEDAGToDAGISel::ID = 0; +INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Offset) { if (Addr.getOpcode() == ISD::FrameIndex) diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index 09421c3..f12bd0f 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -28,6 +28,9 @@ using namespace llvm; extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() { // Register the target. RegisterTargetMachine X(getTheVETarget()); + + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeVEDAGToDAGISelPass(PR); } static std::string computeDataLayout(const Triple &T) { diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index aee8f16..53be8f5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -57,31 +57,32 @@ FunctionPass *createWebAssemblyPeephole(); ModulePass *createWebAssemblyMCLowerPrePass(); // PassRegistry initialization declarations. -void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &); -void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &); void initializeFixFunctionBitcastsPass(PassRegistry &); void initializeOptimizeReturnedPass(PassRegistry &); +void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &); void initializeWebAssemblyArgumentMovePass(PassRegistry &); -void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &); -void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &); -void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &); -void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &); -void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &); -void initializeWebAssemblyRegStackifyPass(PassRegistry &); -void initializeWebAssemblyRegColoringPass(PassRegistry &); -void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &); -void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &); -void initializeWebAssemblyLateEHPreparePass(PassRegistry &); -void initializeWebAssemblyExceptionInfoPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); +void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); +void initializeWebAssemblyDebugFixupPass(PassRegistry &); +void initializeWebAssemblyExceptionInfoPass(PassRegistry &); void initializeWebAssemblyExplicitLocalsPass(PassRegistry &); +void initializeWebAssemblyFixBrTableDefaultsPass(PassRegistry &); +void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &); +void initializeWebAssemblyLateEHPreparePass(PassRegistry &); void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &); -void initializeWebAssemblyRegNumberingPass(PassRegistry &); -void initializeWebAssemblyDebugFixupPass(PassRegistry &); -void initializeWebAssemblyPeepholePass(PassRegistry &); -void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &); +void initializeWebAssemblyLowerEmscriptenEHSjLjPass(PassRegistry &); void initializeWebAssemblyLowerRefTypesIntPtrConvPass(PassRegistry &); +void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &); +void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &); +void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &); +void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &); +void initializeWebAssemblyPeepholePass(PassRegistry &); +void initializeWebAssemblyRegColoringPass(PassRegistry &); +void initializeWebAssemblyRegNumberingPass(PassRegistry &); +void initializeWebAssemblyRegStackifyPass(PassRegistry &); +void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &); +void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &); namespace WebAssembly { enum TargetIndex { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index 15c6629..df79e55 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -29,6 +29,7 @@ using namespace llvm; #define DEBUG_TYPE "wasm-isel" +#define PASS_NAME "WebAssembly Instruction Selection" //===--------------------------------------------------------------------===// /// WebAssembly-specific code to select WebAssembly machine instructions for @@ -43,14 +44,12 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel { public: static char ID; + WebAssemblyDAGToDAGISel() = delete; + WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} - StringRef getPassName() const override { - return "WebAssembly Instruction Selection"; - } - bool runOnMachineFunction(MachineFunction &MF) override { LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n" "********** Function: " @@ -86,6 +85,8 @@ private: char WebAssemblyDAGToDAGISel::ID; +INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + void WebAssemblyDAGToDAGISel::PreprocessISelDAG() { // Stack objects that should be allocated to locals are hoisted to WebAssembly // locals when they are first used. However for those without uses, we hoist diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index bced56f..6bab767 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -82,6 +82,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() { initializeWebAssemblyMCLowerPrePassPass(PR); initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR); initializeWebAssemblyFixBrTableDefaultsPass(PR); + initializeWebAssemblyDAGToDAGISelPass(PR); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h index 6118775..aae1e34 100644 --- a/llvm/lib/Target/XCore/XCore.h +++ b/llvm/lib/Target/XCore/XCore.h @@ -21,6 +21,7 @@ namespace llvm { class FunctionPass; class ModulePass; + class PassRegistry; class TargetMachine; class XCoreTargetMachine; @@ -30,6 +31,7 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel); ModulePass *createXCoreLowerThreadLocalPass(); + void initializeXCoreDAGToDAGISelPass(PassRegistry &); } // end namespace llvm; diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 9369114..3cb806a 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -31,6 +31,9 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +#define DEBUG_TYPE "xcore-isel" +#define PASS_NAME "XCore DAG->DAG Pattern Instruction Selection" + /// XCoreDAGToDAGISel - XCore specific code to select XCore machine /// instructions for SelectionDAG operations. /// @@ -40,6 +43,8 @@ namespace { public: static char ID; + XCoreDAGToDAGISel() = delete; + XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(ID, TM, OptLevel) {} @@ -69,10 +74,6 @@ namespace { bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) override; - StringRef getPassName() const override { - return "XCore DAG->DAG Pattern Instruction Selection"; - } - // Include the pieces autogenerated from the target description. #include "XCoreGenDAGISel.inc" }; @@ -80,6 +81,8 @@ namespace { char XCoreDAGToDAGISel::ID = 0; +INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) + /// createXCoreISelDag - This pass converts a legalized DAG into a /// XCore-specific DAG, ready for instruction scheduling. /// diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index fe9490a..410c854 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -106,6 +106,8 @@ void XCorePassConfig::addPreEmitPass() { // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() { RegisterTargetMachine X(getTheXCoreTarget()); + PassRegistry &PR = *PassRegistry::getPassRegistry(); + initializeXCoreDAGToDAGISelPass(PR); } TargetTransformInfo -- 2.7.4