From 19712d403c3b54518cd34287225c3961e6f9998d Mon Sep 17 00:00:00 2001 From: Zhiwei Yuan Date: Fri, 23 Nov 2018 22:33:36 +0800 Subject: [PATCH] dtv_demod: add DTV demod driver for tl1 [1/1] PD#172587 Problem: add DTV demod driver for tl1 Solution: add DTV demod driver for tl1 Verify: verified by t962x2_x301 Change-Id: I27e88090aa51c0385867cee4d31a5a75192cf650 Signed-off-by: Zhiwei Yuan --- MAINTAINERS | 10 +- arch/arm/boot/dts/amlogic/tl1_pxp.dts | 25 + arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts | 33 + arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts | 33 + drivers/amlogic/media/dtv_demod/aml_demod.c | 343 +++++++- drivers/amlogic/media/dtv_demod/amlfrontend.c | 495 ++++++++++-- drivers/amlogic/media/dtv_demod/atsc_func.c | 2 - drivers/amlogic/media/dtv_demod/demod_func.c | 883 +++++++++++++++++++-- drivers/amlogic/media/dtv_demod/dtmb_func.c | 19 +- drivers/amlogic/media/dtv_demod/dvbc_func.c | 2 +- drivers/amlogic/media/dtv_demod/dvbc_v3.c | 64 +- .../media/dtv_demod/include/addr_atsc_cntr.h | 38 + .../media/dtv_demod/include/addr_atsc_cntr_bit.h | 89 +++ .../media/dtv_demod/include/addr_atsc_demod.h | 79 ++ .../media/dtv_demod/include/addr_atsc_demod_bit.h | 363 +++++++++ .../amlogic/media/dtv_demod/include/addr_atsc_eq.h | 98 +++ .../media/dtv_demod/include/addr_atsc_eq_bit.h | 516 ++++++++++++ .../amlogic/media/dtv_demod/include/amlfrontend.h | 32 +- .../amlogic/media/dtv_demod/include/atsc_func.h | 2 + .../amlogic/media/dtv_demod/include/demod_func.h | 33 +- .../amlogic/media/vin/tvin/tvafe/tvafe_general.c | 18 +- include/uapi/linux/dvb/aml_demod.h | 26 + 22 files changed, 3042 insertions(+), 161 deletions(-) create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr.h create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr_bit.h create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_demod.h create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_demod_bit.h create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_eq.h create mode 100644 drivers/amlogic/media/dtv_demod/include/addr_atsc_eq_bit.h diff --git a/MAINTAINERS b/MAINTAINERS index a97d567..5221842 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14477,15 +14477,19 @@ F: drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.c F: drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.h AMLOGIC DTV DEMOD DRIVER -M: Jihong Sui -F: include/uapi/linux/dvb/aml_demod.h -F: drivers/amlogic/media/amldemod/* +M: Jihong Sui +F: include/uapi/linux/dvb/aml_demod.h +F: drivers/amlogic/media/amldemod/* AMLOGIC DTV DEMOD DRIVER M: Jihong Sui F: drivers/amlogic/media/amldemod/* F: drivers/amlogic/media/dtv_demod/* +AMLOGIC DTV DEMOD DRIVER +M: Zhiwei Yuan +F: drivers/amlogic/media/dtv_demod/include/addr_atsc*.h + AMLOGIC DEFENDKEY DRIVER M: Zhongfu Luo F: drivers/amlogic/defendkey/* diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts index 7a47eaa..3befd6c 100644 --- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts +++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts @@ -162,6 +162,31 @@ tdmout_index = <1>; }; + aml_dtv_demod { + compatible = "amlogic, ddemod-tl1"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xff650000 0x4000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + //memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + auge_sound { compatible = "amlogic, tl1-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts index 0a60ce1..a7f86d6 100644 --- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts +++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts @@ -110,6 +110,14 @@ alignment = <0x400000>; }; + demod_reserved:linux,demod { + compatible = "amlogic, demod-mem"; + size = <0x800000>; //8M //100m 0x6400000 + alloc-ranges = <0x0 0x30000000>; + //multi-use; + //no-map; + }; + /*vbi reserved mem*/ vbi_reserved:linux,vbi { compatible = "amlogic, vbi-mem"; @@ -175,6 +183,31 @@ tdmout_index = <1>; }; + aml_dtv_demod { + compatible = "amlogic, ddemod-tl1"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xff650000 0x4000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <0>; + cma_mem_size = <8>; + memory-region = <&demod_reserved>;//<&demod_reserved>; + }; + auge_sound { compatible = "amlogic, tl1-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts index 705c948..98bd373 100644 --- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts +++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts @@ -110,6 +110,15 @@ alignment = <0x400000>; }; + + demod_reserved:linux,demod { + compatible = "amlogic, demod-mem"; + size = <0x800000>; //8M //100m 0x6400000 + alloc-ranges = <0x0 0x30000000>; + //multi-use; + //no-map; + }; + /*vbi reserved mem*/ vbi_reserved:linux,vbi { compatible = "amlogic, vbi-mem"; @@ -175,6 +184,30 @@ tdmout_index = <1>; }; + aml_dtv_demod { + compatible = "amlogic, ddemod-tl1"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xff650000 0x4000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <0>; + cma_mem_size = <8>; + memory-region = <&demod_reserved>;//<&demod_reserved>; + }; + auge_sound { compatible = "amlogic, tl1-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; diff --git a/drivers/amlogic/media/dtv_demod/aml_demod.c b/drivers/amlogic/media/dtv_demod/aml_demod.c index 285f155..5b673ff 100644 --- a/drivers/amlogic/media/dtv_demod/aml_demod.c +++ b/drivers/amlogic/media/dtv_demod/aml_demod.c @@ -39,6 +39,7 @@ /* #include */ #include #include +#include /* #include */ #include @@ -269,6 +270,9 @@ static long aml_demod_ioctl(struct file *file, int strength = 0; struct dvb_frontend *dvbfe; struct aml_tuner_sys *tuner; + //struct aml_tuner_sys tuner_para = {0}; + struct aml_demod_reg arg_t; + //static unsigned int tuner_attach_flg; switch (cmd) { case AML_DEMOD_GET_RSSI: @@ -290,12 +294,37 @@ static long aml_demod_ioctl(struct file *file, case AML_DEMOD_SET_TUNER: pr_dbg("Ioctl Demod Set Tuner.\n"); dvbfe = aml_get_fe();/*get_si2177_tuner();*/ + #if 0 + if (copy_from_user(&tuner_para, (void __user *)arg, + sizeof(struct aml_tuner_sys))) { + pr_dbg("copy error AML_DEMOD_SET_REG\n"); + } else { + //pr_dbg("dvbfe = %p\n",dvbfe); + pr_dbg("tuner mode = %d\n", tuner_para.mode); + if (tuner_attach_flg == 0) { + attach_tuner_demod(); + tuner_attach_flg = 1; + } + + tuner_set_freq(tuner_para.ch_freq); + + if (tuner_para.mode == FE_ATSC) { + tuner_config_atsc(); + tuner_set_atsc_para(); + } else if (tuner_para.mode == FE_DTMB) { + tuner_config_dtmb(); + tuner_set_dtmb_para(); + } else if (tuner_para.mode == FE_QAM) { + tuner_config_qam(); + tuner_set_qam_para(); + } + } + #endif #if 0 /*ary temp for my_tool:*/ - if (dvbfe != NULL) - dvbfe->ops.tuner_ops.set_tuner(dvbfe, &demod_sta, - &demod_i2c, - (struct aml_tuner_sys *) - arg); + if (dvbfe != NULL) { + pr_dbg("calling tuner ops\n"); + dvbfe->ops.tuner_ops.set_params(dvbfe); + } #endif break; @@ -385,12 +414,27 @@ static long aml_demod_ioctl(struct file *file, case AML_DEMOD_SET_REG: /* pr_dbg("Ioctl Set Register\n"); */ - demod_set_reg((struct aml_demod_reg *)arg); + if (copy_from_user(&arg_t, (void __user *)arg, + sizeof(struct aml_demod_reg))) { + pr_dbg("copy error AML_DEMOD_SET_REG\n"); + } else + demod_set_reg(&arg_t); + + //demod_set_reg((struct aml_demod_reg *)arg); break; case AML_DEMOD_GET_REG: /* pr_dbg("Ioctl Get Register\n"); */ - demod_get_reg((struct aml_demod_reg *)arg); + if (copy_from_user(&arg_t, (void __user *)arg, + sizeof(struct aml_demod_reg))) + pr_dbg("copy error AML_DEMOD_GET_REG\n"); + else + demod_get_reg(&arg_t); + + if (copy_to_user((void __user *)arg, &arg_t, + sizeof(struct aml_demod_reg))) { + pr_dbg("copy_to_user copy error AML_DEMOD_GET_REG\n"); + } break; /* case AML_DEMOD_SET_REGS: */ @@ -449,6 +493,289 @@ static const struct file_operations aml_demod_fops = { #endif }; +#if 0 +static int aml_demod_dbg_open(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic Demod debug Open\n"); + return 0; +} + +static int aml_demod_dbg_release(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic Demod debug Release\n"); + return 0; +} + +static unsigned int addr_for_read; +static unsigned int register_val; +static unsigned int symb_rate; +static unsigned int ch_freq; +static unsigned int modulation; +static char *dbg_name[] = { + "demod top r/w", + "dvbc r/w", + "atsc r/w", + "dtmb r/w", + "front r/w", + "isdbt r/w", + "dvbc init", + "atsc init", + "dtmb init", +}; + +unsigned int get_symbol_rate(void) +{// / 1000 + return symb_rate; +} + +unsigned int get_ch_freq(void) +{// / 1000 + return ch_freq; +} + +unsigned int get_modu(void) +{ + return modulation; +} + +/* + *TVFE_VAFE_CTRL0 0x000d0710 + *TVFE_VAFE_CTRL1 0x00003000 + *TVFE_VAFE_CTRL2 0x1fe09e31 + *HHI_DADC_CNTL 0x0030303c + *HHI_DADC_CNTL2 0x00003480 + *HHI_DADC_CNTL3 0x08700b83 + *HHI_VDAC_CNTL1 0x0000000 + + *ADC_PLL_CNTL0 0X012004e0 + *ADC_PLL_CNTL0 0X312004e0 + *ADC_PLL_CNTL1 0X05400000 + *ADC_PLL_CNTL2 0xe1800000 + *ADC_PLL_CNTL3 0x48681c00 + *ADC_PLL_CNTL4 0x88770290 + *ADC_PLL_CNTL5 0x39272000 + *ADC_PLL_CNTL6 0x56540000 + *ADC_PLL_CNTL0 0X111104e0 + */ +static void aml_demod_adc_init(void) +{ + PR_INFO("%s\n", __func__); + demod_init_mutex(); + demod_power_switch(PWR_ON); + //TVFE_VAFE_CTRL0 + demod_set_tvfe_reg(0x000d0710, 0xff654ec0); + //TVFE_VAFE_CTRL1 + demod_set_tvfe_reg(0x00003000, 0xff654ec4); + //TVFE_VAFE_CTRL2 + demod_set_tvfe_reg(0x1fe09e31, 0xff654ec8); + //HHI_DADC_CNTL + dd_tvafe_hiu_reg_write(0x9c, 0x0030303c); + //HHI_DADC_CNTL2 + dd_tvafe_hiu_reg_write(0xa0, 0x00003480); + //HHI_DADC_CNTL3 + //dd_tvafe_hiu_reg_write(0xa8, 0x08700b83); + dd_tvafe_hiu_reg_write(0xa8, 0x08300b83); + //HHI_VDAC_CNTL1 + dd_tvafe_hiu_reg_write(0x2f0, 0x0000000); + //ADC_PLL_CNTL0 + dd_tvafe_hiu_reg_write(0x2c0, 0X012004e0); + dd_tvafe_hiu_reg_write(0x2c0, 0X312004e0); + //ADC_PLL_CNTL1 + dd_tvafe_hiu_reg_write(0x2c4, 0X05400000); + //ADC_PLL_CNTL2 + //dd_tvafe_hiu_reg_write(0x2c8, 0xe1800000); + dd_tvafe_hiu_reg_write(0x2c8, 0xE0800000);//shijie modify, crystal 24M + //dd_tvafe_hiu_reg_write(0x2c8, 0xe9800000); + //ADC_PLL_CNTL3 + dd_tvafe_hiu_reg_write(0x2cc, 0x48681c00); + //ADC_PLL_CNTL4 + dd_tvafe_hiu_reg_write(0x2d0, 0x88770290); + //ADC_PLL_CNTL5 + dd_tvafe_hiu_reg_write(0x2d4, 0x39272000); + //ADC_PLL_CNTL6 + dd_tvafe_hiu_reg_write(0x2d8, 0x56540000); + //ADC_PLL_CNTL0 + dd_tvafe_hiu_reg_write(0x2c0, 0X111104e0); + //zou weihua + dd_tvafe_hiu_reg_write(0x3cc, 0x00800000); + //shijie + dd_tvafe_hiu_reg_write(0x1d0, 0x501);//0x705 + //shixi, switch to demod mode, enable pclk + //demod_write_reg(DEMOD_TOP_REG0, 0x11); + dtvpll_init_flag(1); +} + +static ssize_t aml_demod_dbg_show(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char buf[80]; + ssize_t len = 0; + + #if 1 + len = snprintf(buf, sizeof(buf), "%s :0x%x = %i\n", + dbg_name[addr_for_read >> 28], addr_for_read & 0xff, + register_val); + #else + len = snprintf(buf, sizeof(buf), "%s\n", __func__); + #endif + //demod_read_reg(DEMOD_TOP_REGC); + //dtmb_read_reg(0); + //dd_tvafe_hiu_reg_write(0x9c, 0x0030303c); + PR_INFO("%s\n", __func__); + //PR_INFO("0xec0 = 0x%x\n", dd_tvafe_hiu_reg_read(0x9c)); + //dvbt_read_reg(0x38); + + return simple_read_from_buffer(userbuf, count, ppos, buf, len); +} + +/*echo dbg_md [0xaddr] [val] > /sys/kernel/debug/demod/xxxx*/ +static ssize_t aml_demod_dbg_store(struct file *file, + const char __user *userbuf, size_t count, loff_t *ppos) +{ + char buf[80]; + unsigned int reg, val, dbg_md; + int ret; + + count = min_t(size_t, count, (sizeof(buf)-1)); + if (copy_from_user(buf, userbuf, count)) + return -EFAULT; + + buf[count] = 0; + + ret = sscanf(buf, "%d %x %i", &dbg_md, ®, &val); + aml_demod_adc_init(); + + switch (ret) { + case 1://cmd + switch (dbg_md) { + case AML_DBG_DVBC_INIT: + Gxtv_Demod_Dvbc_v4_Init(); + break; + case AML_DBG_ATSC_INIT: + demod_set_sys_atsc_v4(); + break; + case AML_DBG_DTMB_INIT: + demod_set_sys_dtmb_v4(); + break; + default: + break; + } + + PR_INFO("%s\n", dbg_name[dbg_md]); + break; + case 2://read register, set param + switch (dbg_md) { + case AML_DBG_DEMOD_TOP_RW: + addr_for_read = (AML_DBG_DEMOD_TOP_RW << 28) | reg; + register_val = demod_read_reg(reg); + break; + case AML_DBG_DVBC_RW: + addr_for_read = (AML_DBG_DVBC_RW << 28) | reg; + register_val = dvbc_read_reg(reg); + break; + case AML_DBG_ATSC_RW: + addr_for_read = (AML_DBG_ATSC_RW << 28) | reg; + register_val = atsc_read_reg_v4(reg); + break; + case AML_DBG_DTMB_RW: + addr_for_read = (AML_DBG_DTMB_RW << 28) | reg; + register_val = dtmb_read_reg(reg); + break; + case AML_DBG_FRONT_RW: + addr_for_read = (AML_DBG_FRONT_RW << 28) | reg; + register_val = front_read_reg_v4(reg); + break; + case AML_DBG_ISDBT_RW: + addr_for_read = (AML_DBG_ISDBT_RW << 28) | reg; + register_val = isdbt_read_reg_v4(reg); + break; + case AML_DBG_DEMOD_SYMB_RATE: + symb_rate = reg; + break; + case AML_DBG_DEMOD_CH_FREQ: + ch_freq = reg; + break; + case AML_DBG_DEMOD_MODUL: + modulation = reg; + break; + default: + break; + } + + PR_INFO("%s reg:0x%x\n", dbg_name[dbg_md], reg); + break; + case 3://write register + switch (dbg_md) { + case AML_DBG_DEMOD_TOP_RW: + demod_write_reg(reg, val); + break; + case AML_DBG_DVBC_RW: + dvbc_write_reg(reg, val); + break; + case AML_DBG_ATSC_RW: + atsc_write_reg_v4(reg, val); + break; + case AML_DBG_DTMB_RW: + dtmb_write_reg(reg, val); + break; + case AML_DBG_FRONT_RW: + front_write_reg_v4(reg, val); + break; + case AML_DBG_ISDBT_RW: + isdbt_write_reg_v4(reg, val); + break; + default: + break; + } + + PR_INFO("%s reg:0x%x,val=%d\n", dbg_name[dbg_md], reg, val); + break; + default: + return -EINVAL; + } + + return count; +} + +static const struct file_operations aml_demod_dvbc_dbg_fops = { + .owner = THIS_MODULE, + .open = aml_demod_dbg_open, + .release = aml_demod_dbg_release, + //.unlocked_ioctl = aml_demod_ioctl, + .read = aml_demod_dbg_show, + .write = aml_demod_dbg_store, +}; + +static void aml_demod_dbg_init(void) +{ + struct dentry *root_entry = dtvdd_devp->demod_root; + struct dentry *entry; + + PR_INFO("%s\n", __func__); + + root_entry = debugfs_create_dir("frontend", NULL); + if (!root_entry) { + PR_INFO("Can't create debugfs dir frontend.\n"); + return; + } + + entry = debugfs_create_file("demod", S_IFREG | 0644, root_entry, NULL, + &aml_demod_dvbc_dbg_fops); + if (!entry) { + PR_INFO("Can't create debugfs file demod.\n"); + return; + } +} + +static void aml_demod_dbg_exit(void) +{ + struct dentry *root_entry = dtvdd_devp->demod_root; + + if (dtvdd_devp && root_entry) + debugfs_remove_recursive(root_entry); +} +#endif + static int aml_demod_ui_open(struct inode *inode, struct file *file) { pr_dbg("Amlogic aml_demod_ui_open Open\n"); @@ -662,6 +989,7 @@ static int __init aml_demod_init(void) sdio_init(); #endif aml_demod_ui_init(); + //aml_demod_dbg_init(); return 0; @@ -701,6 +1029,7 @@ static void __exit aml_demod_exit(void) class_unregister(&aml_demod_class); aml_demod_exit_ui(); + //aml_demod_dbg_exit(); } #ifndef CONFIG_AM_DEMOD_DVBAPI diff --git a/drivers/amlogic/media/dtv_demod/amlfrontend.c b/drivers/amlogic/media/dtv_demod/amlfrontend.c index 8337e0b..4fb2e22 100644 --- a/drivers/amlogic/media/dtv_demod/amlfrontend.c +++ b/drivers/amlogic/media/dtv_demod/amlfrontend.c @@ -39,7 +39,6 @@ #include #include - #ifdef ARC_700 #include #else @@ -158,6 +157,7 @@ const char *name_ic[] = { "txlx", "gxlx", "txhd", + "tl1", }; #define END_SYS_DELIVERY 19 @@ -197,7 +197,6 @@ static void dtvdemod_set_agc_pinmux(int on); static int Gxtv_Demod_Dvbc_Init(/*struct aml_fe_dev *dev, */int mode); - static ssize_t dvbc_auto_sym_show(struct class *cls, struct class_attribute *attr, char *buf) { @@ -709,11 +708,16 @@ static int amdemod_stat_islock(/*struct aml_fe_dev *dev,*/ int mode) if ((atsc_read_iqr_reg() >> 16) == 0x1f) ret = 1; } else if (atsc_mode == VSB_8) { + if (is_ic_ver(IC_VER_TL1)) { + if (atsc_read_reg_v4(0x2e) >= 0x76) + ret = 1; + } else { atsc_fsm = atsc_read_reg(0x0980); PR_DBGL("atsc status [%x]\n", atsc_fsm); /*return atsc_read_reg(0x0980) >= 0x79;*/ if (atsc_read_reg(0x0980) >= 0x79) ret = 1; + } } else { atsc_fsm = atsc_read_reg(0x0980); PR_DBGL("atsc status [%x]\n", atsc_fsm); @@ -726,7 +730,6 @@ static int amdemod_stat_islock(/*struct aml_fe_dev *dev,*/ int mode) } else if (mode == 4) { /*DTMB*/ - /*return (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1;*/ return dtmb_reg_r_fec_lock(); } @@ -1028,12 +1031,17 @@ static int gxtv_demod_dvbc_set_frontend(struct dvb_frontend *fe) param.mode = amdemod_qam(c->modulation); param.symb_rate = c->symbol_rate / 1000; store_dvbc_qam_mode(c->modulation, param.symb_rate); - if ((param.mode == 3) && (demod_status.tmp != Adc_mode)) { - Gxtv_Demod_Dvbc_Init(/*dev,*/ Adc_mode); - /*pr_dbg("Gxtv_Demod_Dvbc_Init,Adc_mode\n");*/ - } else { - /*Gxtv_Demod_Dvbc_Init(dev,Cry_mode);*/ + + if (!is_ic_ver(IC_VER_TL1)) { + if ((param.mode == 3) && (demod_status.tmp != Adc_mode)) { + Gxtv_Demod_Dvbc_Init(/*dev,*/ Adc_mode); + /*pr_dbg("Gxtv_Demod_Dvbc_Init,Adc_mode\n");*/ + } else { + /*Gxtv_Demod_Dvbc_Init(dev,Cry_mode);*/ + } } + + if (autoflags == 0) { /*pr_dbg("QAM_TUNING mode\n");*/ /*flag=0;*/ @@ -1108,6 +1116,13 @@ static int Gxtv_Demod_Dvbc_Init(/*struct aml_fe_dev *dev, */int mode) sys.demod_clk = Demod_Clk_72M; demod_status.tmp = Cry_mode; } + + if (is_ic_ver(IC_VER_TL1)) { + sys.adc_clk = Adc_Clk_24M; + sys.demod_clk = Demod_Clk_250M; + demod_status.tmp = Cry_mode; + } + demod_status.ch_if = Si2176_5M_If * 1000; PR_DBG("[%s]adc_clk is %d,demod_clk is %d\n", __func__, sys.adc_clk, sys.demod_clk); @@ -1118,6 +1133,194 @@ static int Gxtv_Demod_Dvbc_Init(/*struct aml_fe_dev *dev, */int mode) return 0; } +#if 0 +/*TL1*/ +void Gxtv_Demod_Dvbc_v4_Init(void) +{ + //struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_dvbc dvbc; + int nco_rate; + int tmp; + + //printf("frequency point is(KHz):"); + //scanf("%d", &tmp); + //dvbc.ch_freq = tmp; + //dvbc.ch_freq = 474000; + dvbc.ch_freq = 474000; + //dvbc.mode = tmp; + dvbc.mode = 4;// 0=16QAM, 1=32QAM, 2 = 64QAM, 3 = 128QAM, 4 = 256QAM + //dvbc.symb_rate = tmp; + dvbc.symb_rate = 5360;//6875;5056(J.83b 64QAM),5360(J.83b 256QAM) + //ioctl(fd, AML_DEMOD_DVBC_SET_CH, &dvbc); + dvbc.dat0 = 24000; + nco_rate = (24*256)/250+2; + + //app_apb_write_reg(0xf00*4,0x88); + demod_write_reg(DEMOD_TOP_REG0, 0x88); + //app_apb_write_reg(0xf08*4,0x201); + demod_write_reg(DEMOD_TOP_REG8, 0x201); + //app_apb_write_reg(0xf0c*4,0x11); //open write enable + demod_write_reg(DEMOD_TOP_REGC, 0x11); + //app_apb_write_reg(0xe20, + //((app_apb_read_reg(0xe20) &~ 0xff) | (nco_rate & 0xff))); + //app_apb_write_reg(0xe20, (app_apb_read_reg(0xe20) | (1 << 8))); + front_write_reg_v4(0x20, + ((front_read_reg_v4(0x20) & ~0xff) | (nco_rate & 0xff))); + front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8))); + + //dvbc_reg_initial_tmp(&dvbc); + dvbc_reg_initial_tmp_v4(&dvbc); + + //printf("set J.83B(1) OR DVBC(2)"); + tmp = 2; + if (tmp == 1) { + //app_apb_write_reg(reg_reset,0x10f33); + qam_write_reg(0x7, 0x10f33); + //set_j83b_filter_reg(); + set_j83b_filter_reg_v4(); + } else { + //app_apb_write_reg(reg_reset,0xf33); + qam_write_reg(0x7, 0xf33); + } + + #if 0 + printf("select 0~3 mode:"); + scanf("%d", &tmp); + if (tmp == 0) { + //set_dvbc_reg_1(); + set_dvbc_reg_1_v4(); + //set_dvbc_reg_2(); + set_dvbc_reg_2_v4(); + } else if (tmp == 1) { + //set_dvbc_reg_1(); + set_dvbc_reg_1_v4(); + //set_j83b_reg_2(); + set_j83b_reg_2_v4(); + } else if (tmp == 2) { + //set_j83b_reg_1(); + set_j83b_reg_1_v4(); + //set_dvbc_reg_2(); + set_dvbc_reg_2_v4(); + } else if (tmp == 3) { + //set_j83b_reg_1(); + set_j83b_reg_1_v4(); + //set_j83b_reg_2(); + set_j83b_reg_2_v4(); + } + #endif + + #if 0 + app_apb_write_reg(0x48, 0x50e1000); + app_apb_write_reg(0xc0, 0x41f2f69); + #else + qam_write_reg(0x12, 0x50e1000); + qam_write_reg(0x30, 0x41f2f69); + #endif +} + +int uart_error_confirm(int a_0, int a_1) +{ + int flag_out_of_range; + int flag_error; + int flag_zero; + int flag_sta_check; + int st[2]; + int out; + + st[0] = a_0&0xf; + st[1] = (a_0>>4)&0xf; + if (st[1] == 0) + flag_sta_check = ((st[0] == 1) || (st[0] == 2)) ? 0 : 1; + if (st[1] == 1) + flag_sta_check = ((st[0] == 2) || (st[0] == 3)) ? 0 : 1; + if (st[1] == 2) + flag_sta_check = (st[0] == 3) ? 0 : 1; + if (st[1] == 3) + flag_sta_check = (st[0] == 4) ? 0 : 1; + if (st[1] == 4) + flag_sta_check = (st[0] == 6) ? 0 : 1; + if (st[1] == 6) + flag_sta_check = ((st[0] == 4) || (st[0] == 5)) ? 0 : 1; + + flag_zero = (a_0 == 0) ? 1 : 0; + flag_out_of_range = ((a_0 & 0xf) > 6) ? 1 : 0; + flag_error = (((a_0 >> 4) & 0x0fffffff) == (a_1 & 0x0fffffff)) ? 0 : 1; + out = ((flag_out_of_range == 1) || (flag_error == 1) + || (flag_zero == 1)) ? 1 : 0; + return out; +} + +void print_dvbc_result(void) +{ + //int timer1, + int time; + int i, tmp; + //float ftmp; + //struct aml_demod_sts sts; + int status[2], uart_error; + int record = 6, cnt = 0, cur_res = 0; + + //timer1 = read_time_usecond(); + status[0] = status[1] = 0; + time = 1; + i = 0; + while (i < time) { + status[0] = qam_read_reg(0x31); + //if((status[0]&0xf) == 5){ + // timer2=read_time_usecond(); + // printf("\n\n\n\n[sync timer]%d\n",timer2-timer1); + // break; + //} + uart_error = uart_error_confirm(status[0], status[1]); + usleep_range(10000, 10001); + status[1] = status[0]; + i = i + 1; + + //lg add state cnt + cur_res = status[1] & 0xf; + if (cur_res != 6) { + record = cur_res; + } else { + if (record != cur_res) + cnt++; + record = cur_res; + } + + // ioctl(fd, AML_DEMOD_DVBC_GET_CH, &sts); + //tmp = sts.ch_sts; + PR_INFO("sta %08x ulock_n %d ", qam_read_reg(0x6), cnt); + //ftmp = sts.ch_snr; + //ftmp /= 100.0; + //ftmp=(app_apb_read_reg(0x174)&0xfff0)/16/32; + //ftmp=(dvbc_read_reg(0x174)&0xfff0)/16/32; + //PR_INFO("snr %5.2f dB ", ftmp); + PR_INFO("eq status is %d ", qam_read_reg(0x5d)&0xf); + PR_INFO("npn_det %d impdet %d imp_n %d ", + qam_read_reg(0x58)>>20&0x1, qam_read_reg(0x58)>>16&0x3, + qam_read_reg(0x58)&0xffff); + // ftmp = sts.ch_ber; + // ftmp /= 1e6; + // printf("ber %.2e ", ftmp); + // if(ber_avg == 0) + // ber_avg = ftmp; + // ber_avg = ber_avg + (ftmp-ber_avg)/32; + // printf("beravg %.2e ", ber_avg); + tmp = (qam_read_reg(0x33)&0xffff); + //tmp = sts.ch_per; + PR_INFO("per %d ", tmp); + //ftmp=(dvbc_read_reg(0x34)&0xffff)/1e3; + // ftmp = sts.symb_rate; + //PR_INFO("srate %.3f ", ftmp); + //ftmp = (dvbc_read_reg(0x28)&0x7fffff)/1e3; + //PR_INFO("freqoff %.3f kHz ", ftmp); + tmp = (qam_read_reg(0x27)); + //PR_INFO("power %ddb,gain %.3d ", + //((tmp>>22) & 0x1ff)/16.0, tmp & 0x7ff); + PR_INFO("lock sta %x\n", qam_read_reg(0x6)); + } +} +#endif + static void gxtv_demod_dvbt_release(struct dvb_frontend *fe) { @@ -1385,10 +1588,13 @@ static int gxtv_demod_atsc_read_status && (atsc_flag == VSB_8)) { /*atsc_thread();*/ s = amdemod_atsc_stat_islock(); - if ((s == 0) && (last_lock == 1) - && (atsc_read_reg(0x0980) >= 0x76)) { - s = 1; - PR_ATSC("[rsj] unlock,but fsm >= 0x76\n"); + + if (!is_ic_ver(IC_VER_TL1)) { + if ((s == 0) && (last_lock == 1) + && (atsc_read_reg(0x0980) >= 0x76)) { + s = 1; + PR_ATSC("[rsj] unlock,but fsm >= 0x76\n"); + } } } #if 0 /*debug only move to end*/ @@ -1408,8 +1614,17 @@ static int gxtv_demod_atsc_read_status FE_HAS_VITERBI | FE_HAS_SYNC; } else { ilock = 0; - - *status = FE_TIMEDOUT; + if (is_ic_ver(IC_VER_TL1)) { + if (timer_not_enough(D_TIMER_DETECT)) { + *status = 0; + PR_DBG("s=0\n"); + } else { + *status = FE_TIMEDOUT; + timer_disable(D_TIMER_DETECT); + } + } else { + *status = FE_TIMEDOUT; + } #if 0 if (ats_thread_flg) *status = FE_TIMEDOUT; @@ -1418,9 +1633,9 @@ static int gxtv_demod_atsc_read_status #endif } -#if 0 /*debug only*/ +#if 1 /*debug only*/ if (last_lock != ilock) { - pr_error("%s.\n", + PR_INFO("%s.\n", ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!"); last_lock = ilock; } @@ -1518,6 +1733,9 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe) struct aml_demod_atsc param_atsc; struct aml_demod_dvbc param_j83b; int temp_freq = 0; + union ATSC_DEMOD_REG_0X6A_BITS Val_0x6a; + union ATSC_CNTR_REG_0X20_BITS Val_0x20; + int nco_rate; memset(¶m_atsc, 0, sizeof(param_atsc)); memset(¶m_j83b, 0, sizeof(param_j83b)); @@ -1534,7 +1752,9 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe) if (atsc_flag != QAM_AUTO) atsc_flag = QAM_AUTO; /* demod_set_demod_reg(0x502, TXLX_ADC_REG6);*/ - dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x502); + if (!is_ic_ver(IC_VER_TL1)) + dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x502); + demod_set_mode_ts(Gxtv_Dvbc); param_j83b.ch_freq = c->frequency / 1000; param_j83b.mode = amdemod_qam(c->modulation); @@ -1544,17 +1764,64 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe) param_j83b.symb_rate = 5361; else param_j83b.symb_rate = 5361; + + if (is_ic_ver(IC_VER_TL1)) { + nco_rate = ((demod_status.adc_freq / 1000) * 256) + / 250 + 2; + front_write_reg_v4(0x20, + ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + } + dvbc_set_ch(&demod_status, /*&demod_i2c, */¶m_j83b); + + if (is_ic_ver(IC_VER_TL1)) { + qam_write_reg(0x7, 0x10f33); + set_j83b_filter_reg_v4(); + qam_write_reg(0x12, 0x50e1000); + qam_write_reg(0x30, 0x41f2f69); + } + } else if (c->modulation > QAM_AUTO) { - if (atsc_flag != VSB_8) - atsc_flag = VSB_8; - /*demod_set_demod_reg(0x507, TXLX_ADC_REG6);*/ - dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x507); - demod_set_mode_ts(Gxtv_Atsc); - param_atsc.ch_freq = c->frequency / 1000; - param_atsc.mode = c->modulation; - atsc_set_ch(&demod_status, /*&demod_i2c,*/ ¶m_atsc); + if (is_ic_ver(IC_VER_TL1)) { + //demod_set_sys_atsc_v4(); + Val_0x6a.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6A); + Val_0x6a.b.peak_thd = 0x6;//Let CCFO Quality over 6 + atsc_write_reg_v4(ATSC_DEMOD_REG_0X6A, Val_0x6a.bits); + atsc_write_reg_v4(ATSC_EQ_REG_0XA5, 0x8c); + + if (demod_status.adc_freq == Adc_Clk_24M) { + atsc_write_reg_v4(ATSC_DEMOD_REG_0X54, + 0x1aaaaa); + + atsc_write_reg_v4(ATSC_DEMOD_REG_0X55, + 0x3ae28d); + + atsc_write_reg_v4(ATSC_DEMOD_REG_0X6E, + 0x16e3600); + } + + Val_0x20.bits = atsc_read_reg_v4(ATSC_CNTR_REG_0X20); + Val_0x20.b.cpu_rst = 1; + atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits); + Val_0x20.b.cpu_rst = 0; + atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits); + usleep_range(5000, 5001); + } else { + if (atsc_flag != VSB_8) + atsc_flag = VSB_8; + /*demod_set_demod_reg(0x507, TXLX_ADC_REG6);*/ + dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x507); + demod_set_mode_ts(Gxtv_Atsc); + param_atsc.ch_freq = c->frequency / 1000; + param_atsc.mode = c->modulation; + atsc_set_ch(&demod_status, /*&demod_i2c,*/ ¶m_atsc); + } } + + if (is_ic_ver(IC_VER_TL1)) + return 0; + if ((auto_search_std == 1) && ((c->modulation <= QAM_AUTO) && (c->modulation != QPSK))) { unsigned char s = 0; @@ -1661,10 +1928,16 @@ void atsc_detect_first(struct dvb_frontend *fe, enum fe_status *status) check_ok = 0; for (cnt = 0; cnt < CNT_FIRST_ATSC; cnt++) { - gxtv_demod_atsc_read_ucblocks(fe, &ucblocks); + if (!is_ic_ver(IC_VER_TL1)) + gxtv_demod_atsc_read_ucblocks(fe, &ucblocks); gxtv_demod_atsc_read_status(fe, &s); + if (is_ic_ver(IC_VER_TL1)) { + *status = s; + break; + } + // *status = s; if (s != 0x1f) { @@ -1720,6 +1993,11 @@ static int atsc_j83b_detect_first(struct dvb_frontend *fe, enum fe_status *s) for (cnt = 0; cnt < CNT_FIRST; cnt++) { gxtv_demod_atsc_read_status(fe, &cs); + if (is_ic_ver(IC_VER_TL1)) { + *s = cs; + return 0; + } + if (cs != 0x1f) { /*msleep(200);*/ PR_DBG("[j.83b] 1\n"); @@ -1821,7 +2099,6 @@ void atsc_polling(struct dvb_frontend *fe, enum fe_status *status) } - static int gxtv_demod_atsc_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, enum fe_status *status) { @@ -1843,6 +2120,9 @@ static int gxtv_demod_atsc_tune(struct dvb_frontend *fe, bool re_tune, /*PR_ATSC("delivery_system=%d\n", aml_demod_delivery_sys);*/ gxtv_demod_atsc_set_frontend(fe); + if (is_ic_ver(IC_VER_TL1)) + timer_begain(D_TIMER_DETECT); + if (c->modulation == QPSK) { PR_ATSC("modulation is QPSK do nothing!"); } else if (c->modulation <= QAM_AUTO) { @@ -1860,7 +2140,15 @@ static int gxtv_demod_atsc_tune(struct dvb_frontend *fe, bool re_tune, return 0; } #endif - atsc_polling(fe, status); + if (is_ic_ver(IC_VER_TL1)) { + if (c->modulation > QAM_AUTO) + atsc_detect_first(fe, status); + else if (c->modulation <= QAM_AUTO && + (c->modulation != QPSK)) + atsc_j83b_detect_first(fe, status); + } else { + atsc_polling(fe, status); + } return 0; @@ -2212,7 +2500,8 @@ static int gxtv_demod_dtmb_read_status_old if (is_dtmb_ver(IC_DTMB_V2)) { s = dtmb_check_status_gxtv(fe); } else if (is_dtmb_ver(IC_DTMB_V3)) { - s = dtmb_check_status_txl(fe); + if (!is_ic_ver(IC_VER_TL1)) + s = dtmb_check_status_txl(fe); } else { PR_ERR("%s:not support %d!\n", __func__, get_dtmb_ver()); @@ -2227,7 +2516,18 @@ static int gxtv_demod_dtmb_read_status_old FE_HAS_VITERBI | FE_HAS_SYNC; } else { ilock = 0; - *status = FE_TIMEDOUT; + + if (is_ic_ver(IC_VER_TL1)) { + if (timer_not_enough(D_TIMER_DETECT)) { + *status = 0; + PR_DBG("s=0\n"); + } else { + *status = FE_TIMEDOUT; + timer_disable(D_TIMER_DETECT); + } + } else { + *status = FE_TIMEDOUT; + } } if (last_lock != ilock) { PR_INFO("%s.\n", @@ -2240,6 +2540,7 @@ static int gxtv_demod_dtmb_read_status_old static int gxtv_demod_dtmb_read_ber(struct dvb_frontend *fe, u32 *ber) { + *ber = 0; return 0; } @@ -2288,6 +2589,12 @@ static int gxtv_demod_dtmb_set_frontend(struct dvb_frontend *fe) tuner_set_params(fe); /*aml_fe_analog_set_frontend(fe);*/ msleep(100); /* demod_power_switch(PWR_ON); */ + + #if 0 + if (is_ic_ver(IC_VER_TL1)) + demod_set_sys_dtmb_v4(); + else + #endif dtmb_set_ch(&demod_status, /*&demod_i2c,*/ ¶m); return 0; @@ -2320,6 +2627,9 @@ int Gxtv_Demod_Dtmb_Init(struct amldtvdemod_device_s *dev) if (is_ic_ver(IC_VER_TXL)) { sys.adc_clk = Adc_Clk_25M; sys.demod_clk = Demod_Clk_225M; + } else if (is_ic_ver(IC_VER_TL1)) { + sys.adc_clk = Adc_Clk_24M; + sys.demod_clk = Demod_Clk_250M; } else { sys.adc_clk = Adc_Clk_24M; sys.demod_clk = Demod_Clk_225M; @@ -2373,6 +2683,11 @@ static int gxtv_demod_dvbc_tune(struct dvb_frontend *fe, bool re_tune, gxtv_demod_dvbc_read_status_timer(fe, status); + #if 0 + if (is_ic_ver(IC_VER_TL1)) + return ret; + #endif + if (*status & FE_HAS_LOCK) { timer_disable(D_TIMER_SET); } else { @@ -2405,7 +2720,14 @@ static int gxtv_demod_dtmb_tune(struct dvb_frontend *fe, bool re_tune, *delay = HZ / 4; gxtv_demod_dtmb_set_frontend(fe); - firstdetet = dtmb_detect_first(); + + if (is_ic_ver(IC_VER_TL1)) { + timer_begain(D_TIMER_DETECT); + firstdetet = 0; + } else { + firstdetet = dtmb_detect_first(); + } + if (firstdetet == 1) { *status = FE_TIMEDOUT; /*polling mode*/ @@ -2533,6 +2855,8 @@ static bool enter_mode(int mode) /*mem_buf = (long *)phys_to_virt(memstart);*/ if (mode == AM_FE_DTMB_N) { Gxtv_Demod_Dtmb_Init(devn); + if (is_ic_ver(IC_VER_TL1)) + timer_set_max(D_TIMER_DETECT, 500); if (devn->cma_flag == 1) { PR_DBG("CMA MODE, cma flag is %d,mem size is %d", devn->cma_flag, devn->cma_mem_size); @@ -2550,16 +2874,21 @@ static bool enter_mode(int mode) devn->act_dtmb = true; dtmb_set_mem_st(memstart_dtmb); - demod_write_reg(DEMOD_REG4, 0x8); - + //?, already set in Gxtv_Demod_Dtmb_Init() + if (!is_ic_ver(IC_VER_TL1)) + demod_write_reg(DEMOD_TOP_REGC, 0x8); } else if (mode == AM_FE_QAM_N) { Gxtv_Demod_Dvbc_Init(/*dev,*/ Adc_mode); + /*The maximum time of signal detection is 3s*/ timer_set_max(D_TIMER_DETECT, 3000); /*reset is 4s*/ timer_set_max(D_TIMER_SET, 4000); } else if (mode == AM_FE_ATSC_N) { Gxtv_Demod_Atsc_Init(); + + if (is_ic_ver(IC_VER_TL1)) + timer_set_max(D_TIMER_DETECT, 4000); } else if (mode == AM_FE_OFDM_N || mode == AM_FE_ISDBT_N) { Gxtv_Demod_Dvbt_Init(); /*The maximum time of signal detection is 2s */ @@ -2606,7 +2935,7 @@ static int leave_mode(int mode) dtmb_poll_stop(); /*polling mode*/ /* close arbit */ - demod_write_reg(DEMOD_REG4, 0x0); + demod_write_reg(DEMOD_TOP_REGC, 0x0); if (devn->cma_flag == 1) dtmb_cma_release(devn); } @@ -2614,7 +2943,7 @@ static int leave_mode(int mode) if (dtvdd_devp->act_dtmb) { dtmb_poll_stop(); /*polling mode*/ /* close arbit */ - demod_write_reg(DEMOD_REG4, 0x0); + demod_write_reg(DEMOD_TOP_REGC, 0x0); dtvdd_devp->act_dtmb = false; } if ((devn->cma_flag == 1) && dtvdd_devp->flg_cma_allc) { @@ -2706,6 +3035,20 @@ const struct meson_ddemod_data data_txhd = { }; +const struct meson_ddemod_data data_tl1 = { + .name = "ddmode_tl1", + .icver = { + .atsc = IC_ATSC_V2, + .dvbt = IC_MD_NONE, + .dtmb = IC_DTMB_V3, + .dvbc = IC_DVBC_V3, + .reserved = 0, + .offset = IC_OFFS_V4, + .ic = IC_VER_TL1, + }, + +}; + static const struct of_device_id meson_ddemod_match[] = { { .compatible = "amlogic, ddemod-gxtvbb", @@ -2722,6 +3065,9 @@ static const struct of_device_id meson_ddemod_match[] = { }, { .compatible = "amlogic, ddemod-txhd", .data = &data_txhd, + }, { + .compatible = "amlogic, ddemod-tl1", + .data = &data_tl1, }, {}, }; @@ -2888,7 +3234,7 @@ int dtvdemod_set_iccfg_by_dts(struct platform_device *pdev) return 0; } -#if (defined CONFIG_AM_DTVDEMOD) /*move to aml_dtv_demod*/ +#if (defined CONFIG_AMLOGIC_DTV_DEMOD) /*move to aml_dtv_demod*/ static int rmem_demod_device_init(struct reserved_mem *rmem, struct device *dev) { unsigned int demod_mem_start; @@ -2946,28 +3292,36 @@ int dtvdemod_init_regaddr_byversion(struct platform_device *pdev) int ret = 0; /*clear*/ - ireg->off_demod = 0x00; + ireg->off_demod_top = 0x00; ireg->off_dvbc = 0x00; ireg->off_dtmb = 0x00; ireg->off_dvbt = 0x00; ireg->off_atsc = 0x00; + ireg->off_front = 0x00; + ireg->off_isdbt = 0x00; if (is_offset_ver(IC_OFFS_V2)) { - ireg->off_demod = 0xc00; - + ireg->off_demod_top = 0xc00; ireg->off_dvbc = 0x400; ireg->off_dtmb = 0x00; } else if (is_offset_ver(IC_OFFS_V3)) { - ireg->off_demod = 0xf00; - + ireg->off_demod_top = 0xf00; ireg->off_dvbc = 0xc00; ireg->off_dtmb = 0x000; ireg->off_dvbt = 0x400; + ireg->off_isdbt = ireg->off_dvbt; ireg->off_atsc = 0x800; + } else if (is_offset_ver(IC_OFFS_V4)) { + ireg->off_demod_top = 0x3c00; + ireg->off_dvbc = 0x1000; + ireg->off_dtmb = 0x0000; + ireg->off_dvbt = 0x0400; + ireg->off_isdbt = 0x0800; + ireg->off_atsc = 0x0c00; + ireg->off_front = 0x3800; } else { PR_ERR("ic_offset_version[%d] is not support!\n", off_ver); - ireg->off_demod = 0xf00; - + ireg->off_demod_top = 0xf00; ireg->off_dvbc = 0xc00; ireg->off_dtmb = 0x000; ireg->off_dvbt = 0x400; @@ -3016,11 +3370,13 @@ void dbg_reg_addr(void) PR_INFO("%s\n", __func__); PR_INFO("reg address offset:\n"); - PR_INFO("\tdemod:\t0x%x\n", ireg->off_demod); + PR_INFO("\tdemod top:\t0x%x\n", ireg->off_demod_top); PR_INFO("\tdvbc:\t0x%x\n", ireg->off_dvbc); PR_INFO("\tdtmb:\t0x%x\n", ireg->off_dtmb); PR_INFO("\tdvbt:\t0x%x\n", ireg->off_dvbt); + PR_INFO("\tisdbt:\t0x%x\n", ireg->off_isdbt); PR_INFO("\tatsc:\t0x%x\n", ireg->off_atsc); + PR_INFO("\tfront:\t0x%x\n", ireg->off_front); PR_INFO("virtual addr:\n"); for (i = 0; i < ES_MAP_ADDR_NUM; i++) @@ -3108,9 +3464,6 @@ static void dtvdemod_vdac_enable(bool on) } } - - - /* platform driver*/ static int aml_dtvdemod_probe(struct platform_device *pdev) { @@ -3119,7 +3472,6 @@ static int aml_dtvdemod_probe(struct platform_device *pdev) PR_INFO("%s\n", __func__); /*memory*/ - dtvdd_devp = kzalloc(sizeof(struct amldtvdemod_device_s), GFP_KERNEL); @@ -4005,6 +4357,7 @@ static int aml_dtvdm_tune(struct dvb_frontend *fe, bool re_tune, *status = 0; return 0; } + if (is_not_active(fe)) { *status = 0; PR_DBGL("tune :not active\n"); @@ -4187,6 +4540,7 @@ static struct dvb_frontend_ops aml_dtvdm_txlx_ops = { .get_frontend_algo = gxtv_demod_txlx_get_frontend_algo, }; + static struct dvb_frontend_ops aml_dtvdm_gxlx_ops = { .delsys = { SYS_DVBC_ANNEX_A }, .info = { @@ -4259,9 +4613,48 @@ static struct dvb_frontend_ops aml_dtvdm_txhd_ops = { }; -struct dvb_frontend *aml_dtvdm_attach(const struct amlfe_exp_config *config) +static struct dvb_frontend_ops aml_dtvdm_tl1_ops = { +#ifdef CONFIG_AMLOGIC_DVB_COMPAT + .delsys = {SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_B, SYS_ATSC, SYS_DTMB, + SYS_ANALOG}, +#else + .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B, SYS_DVBC_ANNEX_A, SYS_DVBT}, +#endif + .info = { + /*in aml_fe, it is 'amlogic dvb frontend' */ + .name = "amlogic dtv demod tl1", + .frequency_min = 51000000, + .frequency_max = 900000000, + .frequency_stepsize = 0, + .frequency_tolerance = 0, /**/ + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .init = aml_dtvdm_init, + .sleep = aml_dtvdm_sleep, + .set_frontend = aml_dtvdm_set_parameters, + .get_frontend = aml_dtvdm_get_frontend, + .get_tune_settings = aml_dtvdm_get_tune_settings, + .read_status = aml_dtvdm_read_status, + .read_ber = aml_dtvdm_read_ber, + .read_signal_strength = aml_dtvdm_read_signal_strength, + .read_snr = aml_dtvdm_read_snr, + .read_ucblocks = aml_dtvdm_read_ucblocks, + .release = aml_dtvdm_release, + .set_property = aml_dtvdm_set_property, + .get_property = aml_dtvdm_get_property, + +/*-------------*/ + .tune = aml_dtvdm_tune, + .get_frontend_algo = gxtv_demod_txlx_get_frontend_algo, +}; +struct dvb_frontend *aml_dtvdm_attach(const struct amlfe_exp_config *config) { int ic_version = get_ic_ver(); @@ -4294,6 +4687,10 @@ struct dvb_frontend *aml_dtvdm_attach(const struct amlfe_exp_config *config) memcpy(&fe->ops, &aml_dtvdm_txhd_ops, sizeof(struct dvb_frontend_ops)); break; + case IC_VER_TL1: + memcpy(&fe->ops, &aml_dtvdm_tl1_ops, + sizeof(struct dvb_frontend_ops)); + break; default: PR_ERR("attach fail! ic=%d\n", ic_version); /*return NULL;*/ diff --git a/drivers/amlogic/media/dtv_demod/atsc_func.c b/drivers/amlogic/media/dtv_demod/atsc_func.c index f2dd86a..d95b1ef 100644 --- a/drivers/amlogic/media/dtv_demod/atsc_func.c +++ b/drivers/amlogic/media/dtv_demod/atsc_func.c @@ -1196,8 +1196,6 @@ void atsc_thread(void) } - - #if 0 static dtmb_cfg_t list_dtmb_v1[99] = { {0x00000000, 0x01, 0}, diff --git a/drivers/amlogic/media/dtv_demod/demod_func.c b/drivers/amlogic/media/dtv_demod/demod_func.c index 42f38f0..b7482d8 100644 --- a/drivers/amlogic/media/dtv_demod/demod_func.c +++ b/drivers/amlogic/media/dtv_demod/demod_func.c @@ -21,10 +21,11 @@ #include #include #include +#include +#include /*#include "acf_filter_coefficient.h"*/ #include - #include @@ -37,21 +38,10 @@ MODULE_PARM_DESC(debug_demod, "\n\t\t Enable frontend debug information"); static int debug_demod; module_param(debug_demod, int, 0644); - - - - - - - - MODULE_PARM_DESC(demod_mobile_power, "\n\t\t demod_mobile_power debug information"); static int demod_mobile_power = 100; module_param(demod_mobile_power, int, 0644); - - - static struct mutex mp; static struct mutex dtvpll_init_lock; static int dtvpll_init; @@ -142,6 +132,11 @@ void adc_dpll_setup(int clk_a, int clk_b, int clk_sys, int dvb_mode) struct dfe_adcpll_para ddemod_pll; int sts_pll; + if (is_ic_ver(IC_VER_TL1)) { + dtvpll_init_flag(1); + return; + } + adc_pll_cntl.d32 = 0; adc_pll_cntl2.d32 = 0; adc_pll_cntl3.d32 = 0; @@ -406,12 +401,12 @@ void adc_dpll_setup(int clk_a, int clk_b, int clk_sys, int dvb_mode) demod_read_demod_reg(ADC_REGD)); PR_DBG("[adc][%x]%x\n", ADC_REGE, demod_read_demod_reg(ADC_REGE)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG1, - demod_read_demod_reg(DEMOD_REG1)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG2, - demod_read_demod_reg(DEMOD_REG2)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG3, - demod_read_demod_reg(DEMOD_REG3)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG0, + demod_read_demod_reg(DEMOD_TOP_REG0)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG4, + demod_read_demod_reg(DEMOD_TOP_REG4)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG8, + demod_read_demod_reg(DEMOD_TOP_REG8)); } else if (is_meson_gxlx_cpu()) { /*demod_set_demod_reg(TXLX_ADC_RESET_VALUE, ADC_REG3);*/ /*demod_set_demod_reg(adc_pll_cntl.d32, ADC_REG1);*/ @@ -467,12 +462,12 @@ void adc_dpll_setup(int clk_a, int clk_b, int clk_sys, int dvb_mode) demod_read_demod_reg(ADC_REG4)); PR_DBG("[adc][%x]%x\n", ADC_REG6, demod_read_demod_reg(ADC_REG6)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG1, - demod_read_demod_reg(DEMOD_REG1)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG2, - demod_read_demod_reg(DEMOD_REG2)); - PR_DBG("[demod][%x]%x\n", DEMOD_REG3, - demod_read_demod_reg(DEMOD_REG3)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG0, + demod_read_demod_reg(DEMOD_TOP_REG0)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG4, + demod_read_demod_reg(DEMOD_TOP_REG4)); + PR_DBG("[demod][%x]%x\n", DEMOD_TOP_REG8, + demod_read_demod_reg(DEMOD_TOP_REG8)); } #endif ddemod_pll.adcpllctl = adc_pll_cntl.d32; @@ -548,6 +543,17 @@ void demod_set_demod_reg(unsigned int data, unsigned int addr) void __iomem *vaddr; mutex_lock(&mp); + vaddr = ioremap((addr), 0x4); + writel(data, vaddr); + iounmap(vaddr); + mutex_unlock(&mp); +} + +void demod_set_tvfe_reg(unsigned int data, unsigned int addr) +{ + void __iomem *vaddr; + + mutex_lock(&mp); /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ vaddr = ioremap((addr), 0x4); writel(data, vaddr); @@ -565,18 +571,27 @@ unsigned int demod_read_demod_reg(unsigned int addr) tmp = readl(vaddr); iounmap(vaddr); mutex_unlock(&mp); -/* printk("[demod][read]%x,data is %x\n",(addr),tmp); */ + return tmp; } void power_sw_hiu_reg(int on) { if (on == PWR_ON) { - dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, - (dd_tvafe_hiu_reg_read(HHI_DEMOD_MEM_PD_REG) & (~0x2fff))); + if (is_ic_ver(IC_VER_TL1)) + dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, 0); + else + dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, + (dd_tvafe_hiu_reg_read(HHI_DEMOD_MEM_PD_REG) + & (~0x2fff))); } else { - dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, - (dd_tvafe_hiu_reg_read(HHI_DEMOD_MEM_PD_REG) | 0x2fff)); + if (is_ic_ver(IC_VER_TL1)) + dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, + 0xffffffff); + else + dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, + (dd_tvafe_hiu_reg_read + (HHI_DEMOD_MEM_PD_REG) | 0x2fff)); } } @@ -643,6 +658,50 @@ if (is_ic_ver(IC_VER_TXLX) || is_ic_ver(IC_VER_TXHD)) { PR_DBG("[PWR]: GXLX not support power switch,power mem\n"); power_sw_hiu_reg(PWR_ON); +} else if (is_ic_ver(IC_VER_TL1)) { + + if (pwr_cntl == PWR_ON) { + PR_DBG("[PWR]: Power on demod_comp %x,%x\n", + AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0); + /* Powerup demod_comb */ + reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0); + demod_set_ao_reg((reg_data & (~(0x1 << 10))), + AO_RTI_GEN_PWR_SLEEP0); + /* [10] power on */ + /*PR_DBG("[PWR]: Power on demod_comp %x,%x\n",*/ + /* TXLX_HHI_DEMOD_MEM_PD_REG, TXLX_RESET0_LEVEL);*/ + + /* Power up memory */ + power_sw_hiu_reg(PWR_ON); + /* reset */ + power_sw_reset_reg(1); /*reset*/ + /* msleep(20);*/ + + /* remove isolation */ + demod_set_ao_reg( + (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) & + (~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0); + + /* pull up reset */ + power_sw_reset_reg(0); /*reset*/ +/* *P_RESET0_LEVEL |= (0x1<<8); */ + } else { + PR_DBG("[PWR]: Power off demod_comp\n"); + + /* add isolation */ + demod_set_ao_reg( + (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) | + (0x3 << 14)), AO_RTI_GEN_PWR_ISO0); + + /* power down memory */ + power_sw_hiu_reg(PWR_OFF); + /* power down demod_comb */ + reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0); + demod_set_ao_reg((reg_data | (0x1 << 10)), + AO_RTI_GEN_PWR_SLEEP0); + /* [10] power on */ + } + /*} else if (is_meson_gxlx_cpu()) {*/ } else { if (pwr_cntl == PWR_ON) { PR_DBG("[PWR]: Power on demod_comp %x,%x\n", @@ -697,6 +756,10 @@ void demod_set_mode_ts(unsigned char dvb_mode) if (dvb_mode == Gxtv_Dtmb) { cfg0.b.ts_sel = 1; cfg0.b.mode = 1; + if (is_ic_ver(IC_VER_TL1)) { + cfg0.b.adc_format = 0; + cfg0.b.adc_regout = 0; + } } else if (dvb_mode == Gxtv_Dvbt_Isdbt) { cfg0.b.ts_sel = 1<<1; cfg0.b.mode = 1<<1; @@ -706,8 +769,10 @@ void demod_set_mode_ts(unsigned char dvb_mode) cfg0.b.ts_sel = 1<<2; cfg0.b.mode = 1<<2; cfg0.b.adc_format = 0; - cfg0.b.adc_regout = 1; - cfg0.b.adc_regadj = 2; + if (!is_ic_ver(IC_VER_TL1)) { + cfg0.b.adc_regout = 1; + cfg0.b.adc_regadj = 2; + } } else if (dvb_mode == Gxtv_Dvbc) { if (is_dvbc_ver(IC_DVBC_V2)) { cfg0.b.ts_sel = 2; @@ -722,8 +787,7 @@ void demod_set_mode_ts(unsigned char dvb_mode) } } - demod_write_reg(DEMOD_REG1, cfg0.d32); - + demod_write_reg(DEMOD_TOP_REG0, cfg0.d32); } void clocks_set_sys_defaults(unsigned char dvb_mode) @@ -735,19 +799,19 @@ void clocks_set_sys_defaults(unsigned char dvb_mode) tvafe_set_ddemod_default(); demod_set_demod_default(); - sts_pll = adc_set_pll_cntl(1, 0x04, NULL); + if (sts_pll < 0) { /*set pll fail*/ PR_ERR("%s:set pll default fail! please check!\n", __func__); } + demod_set_mode_ts(dvb_mode); cfg2.b.biasgen_en = 1; cfg2.b.en_adc = 1; - - demod_write_reg(DEMOD_REG3, cfg2.d32); + demod_write_reg(DEMOD_TOP_REG8, cfg2.d32); PR_DBG("dvb_mode is %d\n", dvb_mode); - debug_check_reg_val(REG_M_DEMOD, DEMOD_REG1); + debug_check_reg_val(REG_M_DEMOD, DEMOD_TOP_REG0); } #if 0 @@ -774,6 +838,7 @@ void dtmb_write_reg(int reg_addr, int reg_data) { if (!get_dtvpll_init_flag()) return; + mutex_lock(&mp); /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ @@ -791,7 +856,9 @@ unsigned int dtmb_read_reg(unsigned int reg_addr) return 0; mutex_lock(&mp); + tmp = readl(gbase_dtmb() + reg_addr); + mutex_unlock(&mp); return tmp; @@ -802,6 +869,9 @@ unsigned int dtmb_read_reg(unsigned int reg_addr) void dvbt_write_reg(unsigned int addr, unsigned int data) { + if (!get_dtvpll_init_flag()) + return; + mutex_lock(&mp); /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ @@ -814,6 +884,9 @@ unsigned int dvbt_read_reg(unsigned int addr) { unsigned int tmp; + if (!get_dtvpll_init_flag()) + return 0; + mutex_lock(&mp); tmp = readl(gbase_dvbt() + addr); @@ -855,6 +928,36 @@ unsigned int atsc_read_reg(unsigned int reg_addr) return tmp & 0xff; } +/*TL1*/ +void atsc_write_reg_v4(unsigned int addr, unsigned int data) +{ + if (!get_dtvpll_init_flag()) + return; + + mutex_lock(&mp); + /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ + + writel(data, gbase_atsc() + (addr << 2)); + + mutex_unlock(&mp); +} + +unsigned int atsc_read_reg_v4(unsigned int addr) +{ + unsigned int tmp; + + if (!get_dtvpll_init_flag()) + return 0; + + mutex_lock(&mp); + + tmp = readl(gbase_atsc() + (addr << 2)); + + mutex_unlock(&mp); + + return tmp; +} + unsigned int atsc_read_iqr_reg(void) { unsigned int tmp; @@ -872,8 +975,12 @@ unsigned int atsc_read_iqr_reg(void) return tmp & 0xffffffff; } - - +#if 0 +void demod_init_mutex(void) +{ + mutex_init(&mp); +} +#endif int demod_set_sys(struct aml_demod_sta *demod_sta, struct aml_demod_sys *demod_sys) @@ -882,12 +989,14 @@ int demod_set_sys(struct aml_demod_sta *demod_sta, /* demod_sta->tmp=Adc_mode; */ unsigned char dvb_mode; int clk_adc, clk_dem; + int nco_rate; /* int gpioDV_2;*/ /*int gpiW_2;*/ dvb_mode = demod_sta->dvb_mode; clk_adc = demod_sys->adc_clk; clk_dem = demod_sys->demod_clk; + nco_rate = ((clk_adc / 1000) * 256) / 224 + 2; PR_DBG ("demod_set_sys,clk_adc is %d,clk_demod is %d\n", clk_adc, clk_dem); @@ -933,13 +1042,23 @@ int demod_set_sys(struct aml_demod_sta *demod_sta, demod_set_reg_rlt(TXLX_DEMOD_REG4, 0x8); } else if (!is_meson_txlx_cpu()) { /* open arbit */ - /* demod_set_demod_reg(0x8, DEMOD_REG4);*/ + /* demod_set_demod_reg(0x8, DEMOD_TOP_REGC);*/ demod_set_reg_rlt(GXBB_DEMOD_REG4, 0x8); PR_DBG("[open arbit]dtmb\n"); } #else - demod_write_reg(DEMOD_REG4, 0x8); - PR_DBG("[open arbit]dtmb\n"); + if (is_ic_ver(IC_VER_TL1)) { + demod_write_reg(DEMOD_TOP_REGC, 0x11); + front_write_reg_v4(0x20, + ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + + front_write_reg_v4(0x20, + (front_read_reg_v4(0x20) | (1 << 8))); + } else { + demod_write_reg(DEMOD_TOP_REGC, 0x8); + PR_DBG("[open arbit]dtmb\n"); + } #endif /* } else if ((dvb_mode == Gxtv_Dvbt_Isdbt) && is_meson_txlx_cpu()) {*/ } else if ((dvb_mode == Gxtv_Dvbt_Isdbt) && is_ic_ver(IC_VER_TXLX)) { @@ -948,15 +1067,558 @@ int demod_set_sys(struct aml_demod_sta *demod_sta, /*demod_set_demod_reg(0x8, TXLX_DEMOD_REG4);*/ demod_set_reg_rlt(TXLX_DEMOD_REG4, 0x8); #else - demod_write_reg(DEMOD_REG4, 0x8); + demod_write_reg(DEMOD_TOP_REGC, 0x8); #endif PR_DBG("[open arbit]dvbt,txlx\n"); + } else if (is_ic_ver(IC_VER_TL1) && (dvb_mode == Gxtv_Atsc)) { + demod_write_reg(DEMOD_TOP_REGC, 0x11); + front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8))); + } else if (is_ic_ver(IC_VER_TL1) && (dvb_mode == Gxtv_Dvbc)) { + nco_rate = ((clk_adc / 1000) * 256) / 250 + 2; + demod_write_reg(DEMOD_TOP_REGC, 0x11); + front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8))); } + demod_sta->adc_freq = clk_adc; demod_sta->clk_freq = clk_dem; return 0; } +//#ifdef HIGH_MEM +#if 0 +int memorystart = 0x29c00000;//0x35100000;//0x1ef00000;0x9300000 7ca00000 +#endif + +/*TL1*/ +void demod_set_sys_dtmb_v4(void) +{ + #if 0//move to clocks_set_sys_defaults + int nco_rate; + + nco_rate = (24*256)/224+2; + //app_apb_write_reg(0xf00*4,0x11 ); + demod_write_reg(DEMOD_TOP_REG0, 0x11); + //app_apb_write_reg(0xf08*4,0x201); + demod_write_reg(DEMOD_TOP_REG8, 0x201); + //app_apb_write_reg(0xf0c*4,0x11); + demod_write_reg(DEMOD_TOP_REGC, 0x11); + //app_apb_write_reg(0xe20*4, + //((app_apb_read_reg(0xe20*4) &~ 0xff) + //| (nco_rate & 0xff))); + + front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + + //app_apb_write_reg(0xe20*4, (app_apb_read_reg(0xe20*4) | (1 << 8))); + front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8))); + #endif + + //app_apb_write_reg(0x49,memorystart); + //move to enter_mode() + //dtmb_write_reg(DTMB_FRONT_MEM_ADDR, memorystart); + + #if 0//move to dtmb_all_reset() + //app_apb_write_reg(0xe39, (app_apb_read_reg(0xe39) | (1 << 30))); + front_write_reg_v4(0x39, (front_read_reg_v4(0x39) | (1 << 30))); + + + //24M + //app_apb_write_reg(0x25, 0x6aaaaa); + //app_apb_write_reg(0x3e, 0x13196596); + //app_apb_write_reg(0x5b, 0x50a30a25); + dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x6aaaaa); + dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x13196596); + dtmb_write_reg(0x5b << 2, 0x50a30a25); + #endif + + //25m + //app_apb_write_reg(0x25, 0x62c1a5); + //app_apb_write_reg(0x3e, 0x131a747d); + //app_apb_write_reg(0x5b, 0x4d6a0a25); + //dtmb_write_reg(0x25, 0x62c1a5); + //dtmb_write_reg(0x3e, 0x131a747d); + //dtmb_write_reg(0x5b, 0x4d6a0a25); +} + +void demod_set_sys_atsc_v4(void) +{ + //int nco_rate; + #if 0//move to gxtv_demod_atsc_set_frontend() + union ATSC_DEMOD_REG_0X6A_BITS Val_0x6a; + union ATSC_EQ_REG_0XA5_BITS Val_0xa5; + union ATSC_CNTR_REG_0X20_BITS Val_0x20; + union ATSC_DEMOD_REG_0X54_BITS Val_0x54; + union ATSC_DEMOD_REG_0X55_BITS Val_0x55; + union ATSC_DEMOD_REG_0X6E_BITS Val_0x6e; + #endif + + //PR_INFO("%s\n", __func__); + //nco_rate = (24*256)/224+2;// 24 | 25 + //hardware_reset(); + //app_apb_write_reg(0xf0c, 0x10); + //demod_write_reg(DEMOD_TOP_REGC, 0x10);//apb write enable + + #if 0//move to clocks_set_sys_defaults() + //demod_front_init_cmd(); + //app_apb_write_reg(0xf00*4,0x44 ); + demod_write_reg(DEMOD_TOP_REG0, 0x44); + //app_apb_write_reg(0xf08*4,0x201); + demod_write_reg(DEMOD_TOP_REG8, 0x201); + #endif + + #if 0//move to demod_set_sys() + //app_apb_write_reg(0xf0c*4,0x11); + demod_write_reg(DEMOD_TOP_REGC, 0x11); + //app_apb_write_reg(0xe20*4,((app_apb_read_reg(0xe20*4) &~ 0xff) + //| (nco_rate & 0xff))); + front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff) + | (nco_rate & 0xff))); + //app_apb_write_reg(0xe20*4, (app_apb_read_reg(0xe20*4) | (1 << 8))); + front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8))); + #endif + + #if 0//move to gxtv_demod_atsc_set_frontend() + //set_cr_ck_rate(); + //Read Reg + Val_0x6a.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6A); + Val_0xa5.bits = atsc_read_reg_v4(ATSC_EQ_REG_0XA5); + + //24M begin + Val_0x54.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X54); + Val_0x55.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X55); + Val_0x6e.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6E); + //24M end + + //Set Reg + Val_0x6a.b.peak_thd = 0x6;//Let CCFO Quality over 6 + Val_0xa5.bits = 0x8c;//increase state 2 to state 3 + + //24M begin + Val_0x54.bits = 0x1aaaaa;//24m 5m if + Val_0x55.bits = 0x3ae28d;//24m + Val_0x6e.bits = 0x16e3600; + //24M end + + //Write Reg + atsc_write_reg_v4(ATSC_DEMOD_REG_0X6A, Val_0x6a.bits); + atsc_write_reg_v4(ATSC_EQ_REG_0XA5, Val_0xa5.bits); + + //24M begin + atsc_write_reg_v4(ATSC_DEMOD_REG_0X54, Val_0x54.bits); + atsc_write_reg_v4(ATSC_DEMOD_REG_0X55, Val_0x55.bits); + atsc_write_reg_v4(ATSC_DEMOD_REG_0X6E, Val_0x6e.bits); + //24M end + + //atsc_reset(); + Val_0x20.bits = atsc_read_reg_v4(ATSC_CNTR_REG_0X20); + Val_0x20.b.cpu_rst = 1; + atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits); + Val_0x20.b.cpu_rst = 0; + atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits); + usleep_range(5000, 5001); + #endif +} + +/*TL1*/ +void set_j83b_filter_reg_v4(void) +{ + //j83_1 + qam_write_reg(0x40, 0x36333c0d); + qam_write_reg(0x41, 0xa110d01); + qam_write_reg(0x42, 0xf0e4ea7a); + qam_write_reg(0x43, 0x3c0010); + qam_write_reg(0x44, 0x7e0065); + + + //j83_2 + qam_write_reg(0x45, 0xb3a1905); + qam_write_reg(0x46, 0x1c396e07); + qam_write_reg(0x47, 0x3801cc08); + qam_write_reg(0x48, 0x10800a2); + + + qam_write_reg(0x49, 0x53b1f03); + qam_write_reg(0x4a, 0x18377407); + qam_write_reg(0x4b, 0x3401cf0b); + qam_write_reg(0x4c, 0x10d00a1); +} + +#if 0 +/*TL1*/ +void dvbc_reg_initial_tmp_v4(struct aml_demod_dvbc *demod_dvbc) +{ + int clk_freq; + int adc_freq; + int ch_mode; + int agc_mode; + int ch_freq; + int ch_if; + int ch_bw; + int symb_rate; + int phs_cfg; + int afifo_ctr; + int max_frq_off, tmp; + + agc_mode = 1; + ch_if = 5000; + ch_bw = 8000; // kHz + //==important: Chip or FPGA Combo need to change======= + clk_freq = 250000; + adc_freq = 24000; + ch_mode = demod_dvbc->mode; + symb_rate = demod_dvbc->symb_rate; + ch_freq = demod_dvbc->ch_freq; + + //printf("in dvbc_func, clk_freq is %d, adc_freq is %d\n", + //clk_freq, adc_freq); + PR_DBG("in dvbc_func, clk_freq is %d, adc_freq is %d\n", + clk_freq, adc_freq); + + // disable irq + //app_apb_write_reg(0xd0, 0); + qam_write_reg(0x34, 0); + + // reset + //dvbc_reset(); + //app_apb_write_reg(reg_reset, + //app_apb_read_reg(reg_reset) & ~(1 << 4)); // disable fsm_en + qam_write_reg(0x7, + qam_read_reg(0x7) & ~(1 << 4)); // disable fsm_en + //app_apb_write_reg(reg_reset, + //app_apb_read_reg(reg_reset) & ~(1 << 0)); // Sw disable demod + qam_write_reg(0x7, + qam_read_reg(0x7) & ~(1 << 0)); // Sw disable demod + //app_apb_write_reg(reg_reset, + //app_apb_read_reg(reg_reset) | (1 << 0)); // Sw enable demod + qam_write_reg(0x7, + qam_read_reg(0x7) | (1 << 0)); // Sw enable demod + + + //app_apb_write_reg(0x000, 0x00000000); // QAM_STATUS + qam_write_reg(0x000, 0x00000000); // QAM_STATUS + //app_apb_write_reg(reg_reset, 0x00000f00); // QAM_GCTL0 + qam_write_reg(0x7, 0x00000f00); // QAM_GCTL0 + //tmp = app_apb_read_reg(0x008); + tmp = qam_read_reg(0x2); + tmp = (tmp & 0xfffffff8) | ch_mode; + //app_apb_write_reg(0x008, tmp); // qam mode + qam_write_reg(0x2, tmp); // qam mode + + switch (ch_mode) { + case 0: // 16 QAM + #if 0 + app_apb_write_reg(0x1c4, 0xa2200); + app_apb_write_reg(0x1c8, 0xc2b0c49); + app_apb_write_reg(0x1cc, 0x2020000); + app_apb_write_reg(0x1d4, 0xe9178); + app_apb_write_reg(0x1d8, 0x1c100); + app_apb_write_reg(0x1e8, 0x2ab7ff); + app_apb_write_reg(0x24c, 0x641a180c); + app_apb_write_reg(0x250, 0xc141400); + #else + qam_write_reg(0x71, 0xa2200); + qam_write_reg(0x72, 0xc2b0c49); + qam_write_reg(0x73, 0x2020000); + qam_write_reg(0x75, 0xe9178); + qam_write_reg(0x76, 0x1c100); + qam_write_reg(0x7a, 0x2ab7ff); + qam_write_reg(0x93, 0x641a180c); + qam_write_reg(0x94, 0xc141400); + #endif + break; + + case 1: // 32 QAM + #if 0 + app_apb_write_reg(0x1c4, 0x61200); + app_apb_write_reg(0x1c8, 0x99301ae); + app_apb_write_reg(0x1cc, 0x8080000); + app_apb_write_reg(0x1d4, 0xbf10c); + app_apb_write_reg(0x1d8, 0xa05c); + app_apb_write_reg(0x1dc, 0x1000d6); + app_apb_write_reg(0x1e8, 0x19a7ff); + app_apb_write_reg(0x1f0, 0x111222); + app_apb_write_reg(0x1f4, 0x2020305); + app_apb_write_reg(0x1f8, 0x3000d0d); + app_apb_write_reg(0x24c, 0x641f1d0c); + app_apb_write_reg(0x250, 0xc1a1a00); + #else + qam_write_reg(0x71, 0x61200); + qam_write_reg(0x72, 0x99301ae); + qam_write_reg(0x73, 0x8080000); + qam_write_reg(0x75, 0xbf10c); + qam_write_reg(0x76, 0xa05c); + qam_write_reg(0x77, 0x1000d6); + qam_write_reg(0x7a, 0x19a7ff); + qam_write_reg(0x7c, 0x111222); + qam_write_reg(0x7d, 0x2020305); + qam_write_reg(0x7e, 0x3000d0d); + qam_write_reg(0x93, 0x641f1d0c); + qam_write_reg(0x94, 0xc1a1a00); + #endif + break; + + case 2: // 64 QAM + //app_apb_write_reg(0x150, 0x606050d); + // app_apb_write_reg(0x148, 0x346dc); + break; + + case 3: // 128 QAM + #if 0 + app_apb_write_reg(0x1c4, 0x2c200); + app_apb_write_reg(0x1c8, 0xa6e0059); + app_apb_write_reg(0x1cc, 0x8080000); + app_apb_write_reg(0x1d4, 0xa70e9); + app_apb_write_reg(0x1d8, 0x2013); + app_apb_write_reg(0x1dc, 0x35068); + app_apb_write_reg(0x1e0, 0xab100); + app_apb_write_reg(0x1e8, 0xba7ff); + app_apb_write_reg(0x1f0, 0x111222); + app_apb_write_reg(0x1f4, 0x2020305); + app_apb_write_reg(0x1f8, 0x3000d0d); + app_apb_write_reg(0x24c, 0x642a240c); + app_apb_write_reg(0x250, 0xc262600); + #else + qam_write_reg(0x71, 0x2c200); + qam_write_reg(0x72, 0xa6e0059); + qam_write_reg(0x73, 0x8080000); + qam_write_reg(0x75, 0xa70e9); + qam_write_reg(0x76, 0x2013); + qam_write_reg(0x77, 0x35068); + qam_write_reg(0x78, 0xab100); + qam_write_reg(0x7a, 0xba7ff); + qam_write_reg(0x7c, 0x111222); + qam_write_reg(0x7d, 0x2020305); + qam_write_reg(0x7e, 0x3000d0d); + qam_write_reg(0x93, 0x642a240c); + qam_write_reg(0x94, 0xc262600); + #endif + break; + + case 4: // 256 QAM + #if 0 + app_apb_write_reg(0x270, 0x2a232100); + app_apb_write_reg(0x15c, 0x606040d); + #else + qam_write_reg(0x9c, 0x2a232100); + qam_write_reg(0x57, 0x606040d); + #endif + break; + } + + //app_apb_write_reg(0x00c, 0xffff8ffe); // adc_cnt, symb_cnt + qam_write_reg(0x3, 0xffff8ffe); + + #if 0//impossible condition + if (clk_freq == 0) + afifo_ctr = 0; + else + #endif + afifo_ctr = (adc_freq * 256 / clk_freq) + 2; + + #if 0//impossible condition + if (afifo_ctr > 255) + afifo_ctr = 255; + #endif + + #if 0 + app_apb_write_reg(0x010, (afifo_ctr<<16) | 8000); // afifo, rs_cnt_cfg + + app_apb_write_reg(0xe20*4, afifo_ctr | 0x100);//front_end afifo nco rate + app_apb_write_reg(0xe2f*4, 0x0); //front_end sfifo out len + app_apb_write_reg(0x188, 0x2000); //ffe/fbe taps 88/72 + + app_apb_write_reg(0x020, 0x61b53e54);//modified by qiancheng by raymond + #else + qam_write_reg(0x4, (afifo_ctr<<16) | 8000); // afifo, rs_cnt_cfg + + //front_end afifo nco rate + //front_write_reg_v4(0x20, afifo_ctr | 0x100); + //front_write_reg_v4(0x2f, 0x0); //front_end sfifo out len + //dvbc_write_reg(0x188, 0x2000); //ffe/fbe taps 88/72 + + qam_write_reg(0x8, 0x61b53e54); //modified by qiancheng by raymond + #endif + + #if 0//impossible condition + if (adc_freq == 0) { + phs_cfg = 0; + } else { + #endif + // 8*fo/fs*2^20 fo=36.125, fs = 28.57114, = 21d775 + phs_cfg = (1<<31) / adc_freq * ch_if / (1<<8); + //} + + // printk("phs_cfg = %x\n", phs_cfg); + //app_apb_write_reg(0x024, + //0x4c000000 | (phs_cfg&0x7fffff)); // PHS_OFFSET, IF offset, + qam_write_reg(0x9, + 0x4c000000 | (phs_cfg&0x7fffff)); // PHS_OFFSET, IF offset, + + #if 0//impossible condition + if (adc_freq == 0) { + max_frq_off = 0; + } else { + #endif + // max_frq_off = (400KHz * 2^29) / (AD=25 * symbol_rate=68750) + max_frq_off = (1<<29) / symb_rate; + tmp = 40000000 / adc_freq; + max_frq_off = tmp * max_frq_off; + //} + + #if 0 + app_apb_write_reg(0x030, 0x245cf450); //MODIFIED BY QIANCHENG + app_apb_write_reg(0x034, + ((adc_freq & 0xffff) << 16) | (symb_rate&0xffff)); + #else + qam_write_reg(0xc, 0x245cf450); //MODIFIED BY QIANCHENG + qam_write_reg(0xd, + ((adc_freq & 0xffff) << 16) | (symb_rate&0xffff)); + #endif + + //app_apb_write_reg(0x038, 0x00200000); // TIM_SWEEP_RANGE 16000 + + /************* hw state machine config **********/ + //apb_write_reg(0, 0x040, 0x003c); // configure symbol rate step step 0 + + // modified 0x44 0x48 + #if 0 + // blind search, configure max symbol_rate for 7218 fb=3.6M + app_apb_write_reg(0x044, (symb_rate&0xffff)*256); + // configure min symbol_rate fb = 6.95M + app_apb_write_reg(0x048, + ((app_apb_read_reg(0x048)&~(0xff<<8))|3400*256)); + app_apb_write_reg(0x144, (app_apb_read_reg(0x144)&~(0x1<<28))); + #else + // blind search, configure max symbol_rate for 7218 fb=3.6M + qam_write_reg(0x011, (symb_rate&0xffff)*256); + // configure min symbol_rate fb = 6.95M + qam_write_reg(0x12, + ((qam_read_reg(0x12)&~(0xff<<8))|3400*256)); + qam_write_reg(0x51, (qam_read_reg(0x51)&~(0x1<<28))); + #endif + + #if 0//impossible condition + if ((agc_mode & 1) == 0) + // freeze if agc + //app_apb_write_reg(0x094, + //app_apb_read_reg(0x94) | (0x1 << 10)); + // freeze if agc + dvbc_write_reg(0x094, dvbc_read_reg(0x94) | (0x1 << 10)); + #endif + + if ((agc_mode & 2) == 0) // IF control + qam_write_reg(0x25, qam_read_reg(0x25) | (0x1 << 13)); + //app_apb_write_reg(0x098, 0x9fcc8190);//AGC_IFGAIN_CTRL + /* + * AGC_RFGAIN_CTRL 0x0e020800 by raymond, + * if Adjcent channel test, maybe it need change. + */ + //app_apb_write_reg(0x0a0, 0x0e03cd11); + // IMQ, QAM Enable + //app_apb_write_reg(reg_reset, app_apb_read_reg(reg_reset)|0x33); + // IMQ, QAM Enable + qam_write_reg(0x7, qam_read_reg(0x7)|0x33); + + // start hardware machine + //dvbc_sw_reset(0x004, 4); + #if 0 + app_apb_write_reg(reg_reset, app_apb_read_reg(reg_reset) | (1 << 4)); + app_apb_write_reg(0x0e8, (app_apb_read_reg(0x0e8)|(1<<2))); + + // clear irq status + app_apb_read_reg(0xd4); + + // enable irq + app_apb_write_reg(0xd0, 0x7fff<<3); + #else + qam_write_reg(0x7, qam_read_reg(0x7) | (1 << 4)); + qam_write_reg(0x3a, (qam_read_reg(0x3a)|(1<<2))); + + // clear irq status + qam_read_reg(0x35); + + // enable irq + qam_write_reg(0x34, 0x7fff<<3); + #endif +} + +/*TL1*/ +void set_dvbc_reg_1_v4(void) +{ + //dvbc_1 + #if 0 + app_apb_write_reg(0x100, 0x3d3d0002); + app_apb_write_reg(0x104, 0x747f0603); + app_apb_write_reg(0x108, 0xf4130f7a); + app_apb_write_reg(0x10c, 0x1f801d5); + app_apb_write_reg(0x110, 0xc60063); + #else + dvbc_write_reg(0x100, 0x3d3d0002); + dvbc_write_reg(0x104, 0x747f0603); + dvbc_write_reg(0x108, 0xf4130f7a); + dvbc_write_reg(0x10c, 0x1f801d5); + dvbc_write_reg(0x110, 0xc60063); + #endif +} + +/*TL1*/ +void set_dvbc_reg_2_v4(void) +{ + //dvbc_2 + #if 0 + app_apb_write_reg(0x114, 0xc381b06); + app_apb_write_reg(0x118, 0x25346b0a); + app_apb_write_reg(0x11c, 0x3101b90e); + app_apb_write_reg(0x120, 0x17900e5); + #else + dvbc_write_reg(0x114, 0xc381b06); + dvbc_write_reg(0x118, 0x25346b0a); + dvbc_write_reg(0x11c, 0x3101b90e); + dvbc_write_reg(0x120, 0x17900e5); + #endif +} + +/*TL1*/ +void set_j83b_reg_1_v4(void) +{ + //j83_1 + #if 0 + app_apb_write_reg(0x100, 0x3e010201); + app_apb_write_reg(0x104, 0x0b033c3a); + app_apb_write_reg(0x108, 0xe2ecff0c); + app_apb_write_reg(0x10c, 0x002a01f6); + app_apb_write_reg(0x110, 0x0097006a); + #else + dvbc_write_reg(0x100, 0x3e010201); + dvbc_write_reg(0x104, 0x0b033c3a); + dvbc_write_reg(0x108, 0xe2ecff0c); + dvbc_write_reg(0x10c, 0x002a01f6); + dvbc_write_reg(0x110, 0x0097006a); + #endif +} + +/*TL1*/ +void set_j83b_reg_2_v4(void) +{ + //j83_2 + #if 0 + app_apb_write_reg(0x114, 0xb3a1905); + app_apb_write_reg(0x118, 0x1c396e07); + app_apb_write_reg(0x11c, 0x3801cc08); + app_apb_write_reg(0x120, 0x10800a2); + #else + dvbc_write_reg(0x114, 0xb3a1905); + dvbc_write_reg(0x118, 0x1c396e07); + dvbc_write_reg(0x11c, 0x3801cc08); + dvbc_write_reg(0x120, 0x10800a2); + #endif +} +#endif + void demod_set_reg(struct aml_demod_reg *demod_reg) { if (fpga_version == 1) { @@ -1240,7 +1902,6 @@ unsigned int dvbc_read_reg(unsigned int addr) #else void dvbc_write_reg(unsigned int addr, unsigned int data) { - mutex_lock(&mp); /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ @@ -1261,6 +1922,29 @@ unsigned int dvbc_read_reg(unsigned int addr) return tmp; } +void dvbc_write_reg_v4(unsigned int addr, unsigned int data) +{ + + mutex_lock(&mp); + /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ + + writel(data, gbase_dvbc() + (addr << 2)); + + mutex_unlock(&mp); +} +unsigned int dvbc_read_reg_v4(unsigned int addr) +{ + unsigned int tmp; + + mutex_lock(&mp); + + tmp = readl(gbase_dvbc() + (addr << 2)); + + mutex_unlock(&mp); + + return tmp; +} + #endif void demod_write_reg(unsigned int addr, unsigned int data) { @@ -1268,7 +1952,10 @@ void demod_write_reg(unsigned int addr, unsigned int data) mutex_lock(&mp); /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ - writel(data, gbase_demod() + addr); + if (is_ic_ver(IC_VER_TL1)) + writel(data, gbase_demod() + (addr << 2)); + else + writel(data, gbase_demod() + addr); mutex_unlock(&mp); } @@ -1278,11 +1965,69 @@ unsigned int demod_read_reg(unsigned int addr) mutex_lock(&mp); - tmp = readl(gbase_demod() + addr); + if (is_ic_ver(IC_VER_TL1)) + tmp = readl(gbase_demod() + (addr << 2)); + else + tmp = readl(gbase_demod() + addr); + + mutex_unlock(&mp); + + return tmp; +} + +/*TL1*/ +void front_write_reg_v4(unsigned int addr, unsigned int data) +{ + if (!get_dtvpll_init_flag()) + return; + + mutex_lock(&mp); + /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ + + writel(data, gbase_front() + (addr << 2)); + + mutex_unlock(&mp); +} + +unsigned int front_read_reg_v4(unsigned int addr) +{ + unsigned int tmp; + + if (!get_dtvpll_init_flag()) + return 0; + + mutex_lock(&mp); + + tmp = readl(gbase_front() + (addr << 2)); mutex_unlock(&mp); return tmp; + +} + +void isdbt_write_reg_v4(unsigned int addr, unsigned int data) +{ + mutex_lock(&mp); + /* printk("[demod][write]%x,data is %x\n",(addr),data);*/ + + writel(data, gbase_isdbt() + addr); + + mutex_unlock(&mp); +} + +unsigned int isdbt_read_reg_v4(unsigned int addr) +{ + unsigned int tmp; + + mutex_lock(&mp); + + tmp = readl(gbase_isdbt() + addr); + + mutex_unlock(&mp); + + return tmp; + } /*dvbc v3:*/ @@ -1392,24 +2137,26 @@ unsigned int dd_tvafe_reg_read(unsigned int addr) void demod_set_demod_default(void) { + if (is_ic_ver(IC_VER_TL1)) + return; + #if 0 if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) { - demod_set_reg_rlt(GXBB_DEMOD_REG1, DEMOD_REG1_VALUE); - demod_set_reg_rlt(GXBB_DEMOD_REG2, DEMOD_REG2_VALUE); - demod_set_reg_rlt(GXBB_DEMOD_REG3, DEMOD_REG3_VALUE); + demod_set_reg_rlt(GXBB_DEMOD_REG1, DEMOD_REG0_VALUE); + demod_set_reg_rlt(GXBB_DEMOD_REG2, DEMOD_REG4_VALUE); + demod_set_reg_rlt(GXBB_DEMOD_REG3, DEMOD_REG8_VALUE); } else if (is_meson_txlx_cpu() || is_meson_gxlx_cpu() || is_meson_txhd_cpu()) { - demod_set_reg_rlt(TXLX_DEMOD_REG1, DEMOD_REG1_VALUE); - demod_set_reg_rlt(TXLX_DEMOD_REG2, DEMOD_REG2_VALUE); - demod_set_reg_rlt(TXLX_DEMOD_REG3, DEMOD_REG3_VALUE); + demod_set_reg_rlt(TXLX_DEMOD_REG1, DEMOD_REG0_VALUE); + demod_set_reg_rlt(TXLX_DEMOD_REG2, DEMOD_REG4_VALUE); + demod_set_reg_rlt(TXLX_DEMOD_REG3, DEMOD_REG8_VALUE); } #else - demod_write_reg(DEMOD_REG1, DEMOD_REG1_VALUE); - demod_write_reg(DEMOD_REG2, DEMOD_REG2_VALUE); - demod_write_reg(DEMOD_REG3, DEMOD_REG3_VALUE); - + demod_write_reg(DEMOD_TOP_REG0, DEMOD_REG0_VALUE); + demod_write_reg(DEMOD_TOP_REG4, DEMOD_REG4_VALUE); + demod_write_reg(DEMOD_TOP_REG8, DEMOD_REG8_VALUE); #endif } @@ -1477,28 +2224,28 @@ const unsigned int adc_check_tab_gxtvbb[] = { REG_M_HIU, D_HHI_ADC_PLL_CNTL4, /* REG_M_HIU, D_HHI_HDMI_CLK_CNTL, */ - REG_M_DEMOD, DEMOD_REG1, - REG_M_DEMOD, DEMOD_REG2, - REG_M_DEMOD, DEMOD_REG3, - REG_M_DEMOD, DEMOD_REG4, + REG_M_DEMOD, DEMOD_TOP_REG0, + REG_M_DEMOD, DEMOD_TOP_REG4, + REG_M_DEMOD, DEMOD_TOP_REG8, + REG_M_DEMOD, DEMOD_TOP_REGC, /* end */ TABLE_FLG_END, TABLE_FLG_END, }; const unsigned int adc_check_tab_demod_txlx[] = { - REG_M_DEMOD, DEMOD_REG1, - REG_M_DEMOD, DEMOD_REG2, - REG_M_DEMOD, DEMOD_REG3, - REG_M_DEMOD, DEMOD_REG4, + REG_M_DEMOD, DEMOD_TOP_REG0, + REG_M_DEMOD, DEMOD_TOP_REG4, + REG_M_DEMOD, DEMOD_TOP_REG8, + REG_M_DEMOD, DEMOD_TOP_REGC, /* end */ TABLE_FLG_END, TABLE_FLG_END, }; const unsigned int adc_check_tab_demod_gxbb[] = { - REG_M_DEMOD, DEMOD_REG1, - REG_M_DEMOD, DEMOD_REG2, - REG_M_DEMOD, DEMOD_REG3, - REG_M_DEMOD, DEMOD_REG4, + REG_M_DEMOD, DEMOD_TOP_REG0, + REG_M_DEMOD, DEMOD_TOP_REG4, + REG_M_DEMOD, DEMOD_TOP_REG8, + REG_M_DEMOD, DEMOD_TOP_REGC, /* end */ TABLE_FLG_END, TABLE_FLG_END, }; diff --git a/drivers/amlogic/media/dtv_demod/dtmb_func.c b/drivers/amlogic/media/dtv_demod/dtmb_func.c index 13b98ab..21db63b 100644 --- a/drivers/amlogic/media/dtv_demod/dtmb_func.c +++ b/drivers/amlogic/media/dtv_demod/dtmb_func.c @@ -192,9 +192,24 @@ void dtmb_initial(struct aml_demod_sta *demod_sta) /* dtmb_write_reg(0x049, memstart); //only for init */ /*dtmb_spectrum = 1; no use */ dtmb_spectrum = demod_sta->spectrum; - dtmb_register_reset(); - dtmb_all_reset(); + if (is_ic_ver(IC_VER_TL1)) { + front_write_reg_v4(0x39, + (front_read_reg_v4(0x39) | (1 << 30))); + + if (demod_sta->adc_freq == Adc_Clk_24M) { + dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x6aaaaa); + dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x13196596); + dtmb_write_reg(0x5b << 2, 0x50a30a25); + } else if (demod_sta->adc_freq == Adc_Clk_25M) { + dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x62c1a5); + dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x131a747d); + dtmb_write_reg(0x5b << 2, 0x4d6a0a25); + } + } else { + dtmb_register_reset(); + dtmb_all_reset(); + } } int check_dtmb_fec_lock(void) diff --git a/drivers/amlogic/media/dtv_demod/dvbc_func.c b/drivers/amlogic/media/dtv_demod/dvbc_func.c index e4775ca..ca2ac4e 100644 --- a/drivers/amlogic/media/dtv_demod/dvbc_func.c +++ b/drivers/amlogic/media/dtv_demod/dvbc_func.c @@ -350,7 +350,7 @@ int dvbc_set_ch(struct aml_demod_sta *demod_sta, if (demod_sta->ch_if == 0) demod_sta->ch_if = 5000; demod_sta->symb_rate = symb_rate; - if (is_dvbc_ver(IC_DVBC_V3)) + if ((!is_ic_ver(IC_VER_TL1)) && is_dvbc_ver(IC_DVBC_V3)) demod_sta->adc_freq = demod_dvbc->dat0; #if 0 diff --git a/drivers/amlogic/media/dtv_demod/dvbc_v3.c b/drivers/amlogic/media/dtv_demod/dvbc_v3.c index a459920..ab6aeec 100644 --- a/drivers/amlogic/media/dtv_demod/dvbc_v3.c +++ b/drivers/amlogic/media/dtv_demod/dvbc_v3.c @@ -229,7 +229,12 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) switch (ch_mode) { case 0: /*16qam*/ qam_write_reg(0x71, 0x000a2200); - qam_write_reg(0x72, 0x0c2b04a9); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x72, 0xc2b0c49); + else + qam_write_reg(0x72, 0x0c2b04a9); + qam_write_reg(0x73, 0x02020000); qam_write_reg(0x75, 0x000e9178); qam_write_reg(0x76, 0x0001c100); @@ -246,7 +251,12 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) qam_write_reg(0x77, 0x001000d6); qam_write_reg(0x7a, 0x0019a7ff); qam_write_reg(0x7c, 0x00111222); - qam_write_reg(0x7d, 0x05050505); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x7d, 0x2020305); + else + qam_write_reg(0x7d, 0x05050505); + qam_write_reg(0x7e, 0x03000d0d); qam_write_reg(0x93, 0x641f1d0c); qam_write_reg(0x94, 0x0c1a1a00); @@ -261,14 +271,28 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) qam_write_reg(0x76, 0x00002013); qam_write_reg(0x77, 0x00035068); qam_write_reg(0x78, 0x000ab100); - qam_write_reg(0x7a, 0x002ba7ff); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x7a, 0xba7ff); + else + qam_write_reg(0x7a, 0x002ba7ff); + qam_write_reg(0x7c, 0x00111222); - qam_write_reg(0x7d, 0x05050505); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x7d, 0x2020305); + else + qam_write_reg(0x7d, 0x05050505); + qam_write_reg(0x7e, 0x03000d0d); qam_write_reg(0x93, 0x642a240c); qam_write_reg(0x94, 0x0c262600); break; case 4: + if (is_ic_ver(IC_VER_TL1)) { + qam_write_reg(0x9c, 0x2a232100); + qam_write_reg(0x57, 0x606040d); + } break; } /*dvbc_write_reg(QAM_BASE+0x00c, 0xfffffffe);*/ @@ -311,7 +335,11 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) max_frq_off = tmp * max_frq_off; } PR_DVBC("max_frq_off is %x,\n", max_frq_off); - qam_write_reg(0xb, max_frq_off & 0x3fffffff); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0xc, 0x245cf450); //MODIFIED BY QIANCHENG + else + qam_write_reg(0xb, max_frq_off & 0x3fffffff); /* max frequency offset, by raymond 20121208 */ /*dvbc_write_reg(QAM_BASE+0x030, 0x011bf400);*/ @@ -335,6 +363,9 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) /*dvbc_write_reg(QAM_BASE+0x048, 3600*256);*/ /* // configure min symbol_rate fb = 6.95M*/ qam_write_reg(0x12, (qam_read_reg(0x12) & ~(0xff<<8)) | 3400 * 256); + + if (is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x51, (qam_read_reg(0x51)&~(0x1<<28))); /* configure min symbol_rate fb = 6.95M */ /*dvbc_write_reg(QAM_BASE+0x0c0, 0xffffff68); // threshold */ @@ -378,8 +409,9 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) /* if Adjcent channel test, maybe it need change.*/ /*20121208 ad invert*/ /*rsj//qam_write_reg(0x28, 0x0603cd10);*/ - qam_write_reg(0x28, - qam_read_reg(0x28) | (adc_format << 27)); + if (!is_ic_ver(IC_VER_TL1)) + qam_write_reg(0x28, + qam_read_reg(0x28) | (adc_format << 27)); /* AGC_RFGAIN_CTRL 0x0e020800 by raymond,*/ /* if Adjcent channel test, maybe it need change.*/ /* 20121208 ad invert,20130221, suit for two path channel.*/ @@ -425,16 +457,21 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta) qam_auto_scan(1); } #endif - qam_write_reg(0x7, 0x10f23); - qam_write_reg(0x3a, 0x0); - qam_write_reg(0x7, 0x10f33); - qam_write_reg(0x3a, 0x4); + if (!is_ic_ver(IC_VER_TL1)) { + qam_write_reg(0x7, 0x10f23); + qam_write_reg(0x3a, 0x0); + qam_write_reg(0x7, 0x10f33); + qam_write_reg(0x3a, 0x4); + } /*auto track*/ /* dvbc_set_auto_symtrack(); */ } u32 dvbc_set_auto_symtrack(void) { + if (is_ic_ver(IC_VER_TL1)) + return 0; + qam_write_reg(0xc, 0x245bf45c); /*open track */ qam_write_reg(0x8, 0x61b2bf5c); qam_write_reg(0x11, (7000 & 0xffff) * 256); @@ -512,6 +549,11 @@ void dvbc_init_reg_ext(void) { /*ary move from amlfrontend.c */ qam_write_reg(0x7, 0xf33); + + if (is_ic_ver(IC_VER_TL1)) { + qam_write_reg(0x12, 0x50e1000); + qam_write_reg(0x30, 0x41f2f69); + } } u32 dvbc_get_ch_sts(void) diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr.h new file mode 100644 index 0000000..700a162 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr.h @@ -0,0 +1,38 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_CNTR_H__ +#define __ADDR_ATSC_CNTR_H__ + +#include "addr_atsc_cntr_bit.h" + +#define MOD_ATSC_CNTR 0x0 +#define ATSC_CNTR_ADDR(x) (MOD_ATSC_CNTR+(x)) + +#define ATSC_CNTR_REG_0X20 ATSC_CNTR_ADDR(0x20) +#define ATSC_CNTR_REG_0X21 ATSC_CNTR_ADDR(0x21) +#define ATSC_CNTR_REG_0X22 ATSC_CNTR_ADDR(0x22) +#define ATSC_CNTR_REG_0X23 ATSC_CNTR_ADDR(0x23) +#define ATSC_CNTR_REG_0X24 ATSC_CNTR_ADDR(0x24) +#define ATSC_CNTR_REG_0X29 ATSC_CNTR_ADDR(0x29) +#define ATSC_CNTR_REG_0X2A ATSC_CNTR_ADDR(0x2a) +#define ATSC_CNTR_REG_0X2B ATSC_CNTR_ADDR(0x2b) +#define ATSC_CNTR_REG_0X2C ATSC_CNTR_ADDR(0x2c) +#define ATSC_CNTR_REG_0X2D ATSC_CNTR_ADDR(0x2d) +#define ATSC_CNTR_REG_0X2E ATSC_CNTR_ADDR(0x2e) + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr_bit.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr_bit.h new file mode 100644 index 0000000..87d8e47 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr_bit.h @@ -0,0 +1,89 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_cntr_bit.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_CNTR_BIT_H__ +#define __ADDR_ATSC_CNTR_BIT_H__ + +union ATSC_CNTR_REG_0X20_BITS { + unsigned int bits; + struct { + unsigned int cpu_rst :1, + reserved0 :3, + cr_pilot_only :1, + reserved1 :27; + } b; +}; + +struct ATSC_CNTR_REG_0X21_BITS { + unsigned int sys_sm_ow_ctrl :10, + reserved2 :6, + nco_loop_close_dly :10, + reserved3 :6; +}; +struct ATSC_CNTR_REG_0X22_BITS { + unsigned int flock_to_cnt :8, + no_crlock_to :1, + reserved4 :3, + no_snr_to :1, + reserved5 :3, + no_ddm_to :1, + reserved6 :15; +}; +struct ATSC_CNTR_REG_0X23_BITS { + unsigned int flock_cnt_limit :6, + reserved7 :2, + flock_th :6, + reserved8 :2, + pn511_acum_th :16; +}; +struct ATSC_CNTR_REG_0X24_BITS { + unsigned int crdet_mode_sel_div :8, + crdet_mode_sel_ndiv :8, + ffe_tap_pwr_th :10, + reserved9 :6; +}; +struct ATSC_CNTR_REG_0X29_BITS { + unsigned int cw_rg0 :25, + reserved10 :7; +}; +struct ATSC_CNTR_REG_0X2A_BITS { + unsigned int cw_rg1 :25, + reserved11 :7; +}; +struct ATSC_CNTR_REG_0X2B_BITS { + unsigned int cw_rg2 :25, + reserved12 :7; +}; +struct ATSC_CNTR_REG_0X2C_BITS { + unsigned int cw_rg3 :25, + reserved13 :3, + cw_exists :1, + reserved14 :3; +}; +struct ATSC_CNTR_REG_0X2D_BITS { + unsigned int inband_pwr_avg_out :16, + inband_pwr_out :14, + reserved15 :1, + inband_pwr_low_flag :1; +}; +struct ATSC_CNTR_REG_0X2E_BITS { + unsigned int sys_states :4, + eq_states :4, + reserved16 :24; +}; + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod.h new file mode 100644 index 0000000..561b309 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod.h @@ -0,0 +1,79 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_demod.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_DEMOD_H__ +#define __ADDR_ATSC_DEMOD_H__ +#include "addr_atsc_demod_bit.h" + +#define MOD_ATSC_DEMOD 0x0 +#define ATSC_DEMOD_ADDR(x) (MOD_ATSC_DEMOD+(x)) + +#define ATSC_DEMOD_REG_0X52 ATSC_DEMOD_ADDR(0x52) +#define ATSC_DEMOD_REG_0X53 ATSC_DEMOD_ADDR(0x53) +#define ATSC_DEMOD_REG_0X54 ATSC_DEMOD_ADDR(0x54) +#define ATSC_DEMOD_REG_0X55 ATSC_DEMOD_ADDR(0x55) +#define ATSC_DEMOD_REG_0X56 ATSC_DEMOD_ADDR(0x56) +#define ATSC_DEMOD_REG_0X58 ATSC_DEMOD_ADDR(0x58) +#define ATSC_DEMOD_REG_0X59 ATSC_DEMOD_ADDR(0x59) +#define ATSC_DEMOD_REG_0X5A ATSC_DEMOD_ADDR(0x5a) +#define ATSC_DEMOD_REG_0X5B ATSC_DEMOD_ADDR(0x5b) +#define ATSC_DEMOD_REG_0X5C ATSC_DEMOD_ADDR(0x5c) +#define ATSC_DEMOD_REG_0X5D ATSC_DEMOD_ADDR(0x5d) +#define ATSC_DEMOD_REG_0X5E ATSC_DEMOD_ADDR(0x5e) +#define ATSC_DEMOD_REG_0X5F ATSC_DEMOD_ADDR(0x5f) +#define ATSC_DEMOD_REG_0X60 ATSC_DEMOD_ADDR(0x60) +#define ATSC_DEMOD_REG_0X61 ATSC_DEMOD_ADDR(0x61) +#define ATSC_DEMOD_REG_0X62 ATSC_DEMOD_ADDR(0x62) +#define ATSC_DEMOD_REG_0X63 ATSC_DEMOD_ADDR(0x63) +#define ATSC_DEMOD_REG_0X64 ATSC_DEMOD_ADDR(0x64) +#define ATSC_DEMOD_REG_0X65 ATSC_DEMOD_ADDR(0x65) +#define ATSC_DEMOD_REG_0X66 ATSC_DEMOD_ADDR(0x66) +#define ATSC_DEMOD_REG_0X67 ATSC_DEMOD_ADDR(0x67) +#define ATSC_DEMOD_REG_0X68 ATSC_DEMOD_ADDR(0x68) +#define ATSC_DEMOD_REG_0X69 ATSC_DEMOD_ADDR(0x69) +#define ATSC_DEMOD_REG_0X6A ATSC_DEMOD_ADDR(0x6a) +#define ATSC_DEMOD_REG_0X6B ATSC_DEMOD_ADDR(0x6b) +#define ATSC_DEMOD_REG_0X6C ATSC_DEMOD_ADDR(0x6c) +#define ATSC_DEMOD_REG_0X6D ATSC_DEMOD_ADDR(0x6d) +#define ATSC_DEMOD_REG_0X6E ATSC_DEMOD_ADDR(0x6e) +#define ATSC_DEMOD_REG_0X70 ATSC_DEMOD_ADDR(0x70) +#define ATSC_DEMOD_REG_0X71 ATSC_DEMOD_ADDR(0x71) +#define ATSC_DEMOD_REG_0X72 ATSC_DEMOD_ADDR(0x72) +#define ATSC_DEMOD_REG_0X73 ATSC_DEMOD_ADDR(0x73) +#define ATSC_DEMOD_REG_0X74 ATSC_DEMOD_ADDR(0x74) +#define ATSC_DEMOD_REG_0X75 ATSC_DEMOD_ADDR(0x75) +#define ATSC_DEMOD_REG_0X76 ATSC_DEMOD_ADDR(0x76) +#define ATSC_DEMOD_REG_0X77 ATSC_DEMOD_ADDR(0x77) +#define ATSC_DEMOD_REG_0X78 ATSC_DEMOD_ADDR(0x78) +#define ATSC_DEMOD_REG_0X79 ATSC_DEMOD_ADDR(0x79) +#define ATSC_DEMOD_REG_0X7A ATSC_DEMOD_ADDR(0x7a) +#define ATSC_DEMOD_REG_0X7B ATSC_DEMOD_ADDR(0x7b) +#define ATSC_DEMOD_REG_0X7C ATSC_DEMOD_ADDR(0x7c) +#define ATSC_DEMOD_REG_0X7D ATSC_DEMOD_ADDR(0x7d) +#define ATSC_DEMOD_REG_0X7E ATSC_DEMOD_ADDR(0x7e) +#define ATSC_DEMOD_REG_0X7F ATSC_DEMOD_ADDR(0x7f) +#define ATSC_DEMOD_REG_0X80 ATSC_DEMOD_ADDR(0x80) +#define ATSC_DEMOD_REG_0X81 ATSC_DEMOD_ADDR(0x81) +#define ATSC_DEMOD_REG_0X82 ATSC_DEMOD_ADDR(0x82) +#define ATSC_DEMOD_REG_0X83 ATSC_DEMOD_ADDR(0x83) +#define ATSC_DEMOD_REG_0X84 ATSC_DEMOD_ADDR(0x84) +#define ATSC_DEMOD_REG_0X85 ATSC_DEMOD_ADDR(0x85) +#define ATSC_DEMOD_REG_0X86 ATSC_DEMOD_ADDR(0x86) +#define ATSC_DEMOD_REG_0X87 ATSC_DEMOD_ADDR(0x87) +#define ATSC_DEMOD_REG_0X88 ATSC_DEMOD_ADDR(0x88) + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod_bit.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod_bit.h new file mode 100644 index 0000000..be75328 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_demod_bit.h @@ -0,0 +1,363 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_demod_bit.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_DEMOD_BIT_H__ +#define __ADDR_ATSC_DEMOD_BIT_H__ + +struct ATSC_DEMOD_REG_0X52_BITS { + unsigned int lpf_crgn_3 :5, + reserved0 :3, + lpf_crgn_4 :5, + reserved1 :3, + lpf_crgn_5 :5, + reserved2 :3, + lpf_crgn_6 :5, + reserved3 :3; +}; +struct ATSC_DEMOD_REG_0X53_BITS { + unsigned int lpf_crgn_0 :5, + reserved4 :3, + lpf_crgn_1 :5, + reserved5 :3, + lpf_crgn_2 :5, + reserved6 :11; +}; + +union ATSC_DEMOD_REG_0X54_BITS { + unsigned int bits; + struct { + unsigned int cr_rate :23, + reserved7 :9; + } b; +}; +union ATSC_DEMOD_REG_0X55_BITS { + unsigned int bits; + struct { + unsigned int ck_rate :24, + reserved8 :8; + } b; +}; +struct ATSC_DEMOD_REG_0X56_BITS { + unsigned int dc_frz :1, + fagc_frz :1, + inv_spectrum :1, + qam_vsr_frz :1, + ck_rate_frz :1, + no_sym_en_ctrl :1, + cr_open_loop :1, + qam_vsr_sel :1, + dc_rmv_bw :4, + reserved9 :20; +}; +struct ATSC_DEMOD_REG_0X58_BITS { + unsigned int fagc_bw :4, + reserved10 :4, + fagc_ref_level :20, + fagc_ref_level_sel :1, + reserved11 :3; +}; +struct ATSC_DEMOD_REG_0X59_BITS { + unsigned int fs_dly_num :10, + reserved12 :22; +}; +struct ATSC_DEMOD_REG_0X5A_BITS { + unsigned int pk512_th :12, + reserved13 :4, + prescale :3, + reserved14 :13; +}; +struct ATSC_DEMOD_REG_0X5B_BITS { + unsigned int fagc_fix_gain :12, + reserved15 :4, + fcorv_th :8, + reserved16 :8; +}; +struct ATSC_DEMOD_REG_0X5C_BITS { + unsigned int m1m2rate_1 :8, + m1m2rate_2 :8, + m1m2rate_3 :8, + m1m2rate_4 :8; +}; +union ATSC_DEMOD_REG_0X5D_BITS { + unsigned int bits; + struct { + unsigned int fld_conf_cnt :8, + clk_conf_cnt :8, + clk_conf_cnt_limit :8; + } b; +}; +struct ATSC_DEMOD_REG_0X5E_BITS { + unsigned int balance_track_bw :8, + balance_track_dir :1, + reserved17 :3, + balance_track :3, + reserved18 :17; +}; +struct ATSC_DEMOD_REG_0X5F_BITS { + unsigned int div_mix_rate :4, + div_mix_en :1, + reserved19 :27; +}; +struct ATSC_DEMOD_REG_0X60_BITS { + unsigned int cr_stepsize :4, + cr_dc_sum_cnt :4, + cr_enable :1, + reserved20 :23; +}; +union ATSC_DEMOD_REG_0X61_BITS { + unsigned int bits; + struct { + unsigned int cr_bin_freq1 :11, + reserved21 :5, + cr_bin_freq2 :11, + reserved22 :5; + } b; +}; +struct ATSC_DEMOD_REG_0X62_BITS { + unsigned int coef0 :6, + reserved23 :2, + coef1 :6, + reserved24 :2, + coef2 :6, + reserved25 :2, + coef3 :6, + reserved26 :2; +}; +struct ATSC_DEMOD_REG_0X63_BITS { + unsigned int coef4 :6, + reserved27 :2, + coef5 :6, + reserved28 :2, + coef6 :6, + reserved29 :2, + coef7 :6, + reserved30 :2; +}; +struct ATSC_DEMOD_REG_0X64_BITS { + unsigned int coef8 :6, + reserved31 :2, + coef9 :6, + reserved32 :2, + coef10 :6, + reserved33 :2, + coef11 :6, + reserved34 :2; +}; +struct ATSC_DEMOD_REG_0X65_BITS { + unsigned int coef12 :6, + reserved35 :2, + coef13 :7, + reserved36 :1, + coef14 :7, + reserved37 :1, + coef15 :8; +}; +struct ATSC_DEMOD_REG_0X66_BITS { + unsigned int coef16 :8, + reserved38 :24; +}; +struct ATSC_DEMOD_REG_0X67_BITS { + unsigned int coef17 :9, + reserved39 :7, + coef18 :9, + reserved40 :7; +}; +struct ATSC_DEMOD_REG_0X68_BITS { + unsigned int coef19 :10, + reserved41 :6, + coef20 :10, + reserved42 :6; +}; +struct ATSC_DEMOD_REG_0X69_BITS { + unsigned int cf_rnd_bits :2, + reserved43 :30; +}; +union ATSC_DEMOD_REG_0X6A_BITS { + unsigned int bits; + struct{ + unsigned int peak_thd :4, + cfo_alpha :4, + ccfo_intv2 :6, + reserved44 :2, + ccfo_intv1 :6, + reserved45 :2, + ccfo_intv0 :6, + ccfo_do_disable :1, + ccfo_enable :1; + } b; +}; +struct ATSC_DEMOD_REG_0X6B_BITS { + unsigned int ccfo_freq_coef1 :10, + reserved46 :6, + ccfo_freq_coef2 :10, + reserved47 :6; +}; +struct ATSC_DEMOD_REG_0X6C_BITS { + unsigned int ccfo_freq_coef3 :10, + reserved48 :6, + ccfo_freq_coef4 :10, + reserved49 :6; +}; +struct ATSC_DEMOD_REG_0X6D_BITS { + unsigned int ccfo_fs :10, + reserved50 :22; +}; +union ATSC_DEMOD_REG_0X6E_BITS { + unsigned int bits; + struct { + unsigned int adc_fs :26, + reserved51 :6; + } b; +}; +struct ATSC_DEMOD_REG_0X70_BITS { + unsigned int gain_step :8, + gain_step_er :8, + soft_gain_in :12, + reserved52 :4; +}; +struct ATSC_DEMOD_REG_0X71_BITS { + unsigned int dagc_mode :2, + reserved53 :2, + dagc_power_alpha :2, + reserved54 :2, + dagc_out_mux :1, + reserved55 :23; +}; +union ATSC_DEMOD_REG_0X72_BITS { + unsigned int bits; + struct { + unsigned int avg_power :8, + gain_result :12, + dagc_ready :1, + reserved56 :11; + } b; +}; +struct ATSC_DEMOD_REG_0X73_BITS { + unsigned int cr_err_lpf1 :24, + reserved57 :8; +}; +struct ATSC_DEMOD_REG_0X74_BITS { + unsigned int cr_err_lpf2 :19, + reserved58 :13; +}; +struct ATSC_DEMOD_REG_0X75_BITS { + unsigned int clk_offset :21, + reserved59 :11; +}; +struct ATSC_DEMOD_REG_0X76_BITS { + unsigned int agc_sat1 :1, + reserved60 :3, + agc_sat2 :1, + reserved61 :27; +}; +struct ATSC_DEMOD_REG_0X77_BITS { + unsigned int i_dc_out1 :12, + reserved62 :4, + q_dc_out1 :12, + reserved63 :4; +}; +struct ATSC_DEMOD_REG_0X78_BITS { + unsigned int i_dc_out2 :12, + reserved64 :4, + q_dc_out2 :12, + reserved65 :4; +}; +struct ATSC_DEMOD_REG_0X79_BITS { + unsigned int cr_avg_cw1_i :12, + reserved66 :4, + cr_avg_cw1_q :12, + reserved67 :4; +}; +struct ATSC_DEMOD_REG_0X7A_BITS { + unsigned int cr_avg_cw2_i :12, + reserved68 :4, + cr_avg_cw2_q :12, + reserved69 :4; +}; +struct ATSC_DEMOD_REG_0X7B_BITS { + unsigned int phase_shift :23, + reserved70 :1, + qam_phase_err_ctrl :2, + reserved71 :6; +}; +struct ATSC_DEMOD_REG_0X7C_BITS { + unsigned int cr_ofst_gna :15, + reserved72 :17; +}; +struct ATSC_DEMOD_REG_0X7D_BITS { + unsigned int cr_ofst_a2 :17, + reserved73 :15; +}; +struct ATSC_DEMOD_REG_0X7E_BITS { + unsigned int cr_ofst_a1 :18, + reserved74 :14; +}; +struct ATSC_DEMOD_REG_0X7F_BITS { + unsigned int ru_ofst_gna :15, + reserved75 :17; +}; +struct ATSC_DEMOD_REG_0X80_BITS { + unsigned int ru_ofst_a2 :17, + reserved76 :15; +}; +struct ATSC_DEMOD_REG_0X81_BITS { + unsigned int ru_ofst_a1 :18, + reserved77 :14; +}; +struct ATSC_DEMOD_REG_0X82_BITS { + unsigned int fagc_ref_l_eqst0 :8, + fagc_ref_l_eqst1 :8, + fagc_ref_l_eqst2 :8, + fagc_ref_l_eqst3 :8; +}; +struct ATSC_DEMOD_REG_0X83_BITS { + unsigned int fagc_ref_l_eqst4 :8, + fagc_ref_l_eqst5 :8, + fagc_ref_l_eqst6 :8, + fagc_ref_l_eqst7 :8; +}; +struct ATSC_DEMOD_REG_0X84_BITS { + unsigned int fagc_ref_l_eqst8 :8, + fagc_ref_l_eqst9 :8, + reserved78 :16; +}; +struct ATSC_DEMOD_REG_0X85_BITS { + unsigned int fagc_ref_h_eqst0 :8, + fagc_ref_h_eqst1 :8, + fagc_ref_h_eqst2 :8, + fagc_ref_h_eqst3 :8; +}; +struct ATSC_DEMOD_REG_0X86_BITS { + unsigned int fagc_ref_h_eqst4 :8, + fagc_ref_h_eqst5 :8, + fagc_ref_h_eqst6 :8, + fagc_ref_h_eqst7 :8; +}; +struct ATSC_DEMOD_REG_0X87_BITS { + unsigned int fagc_ref_h_eqst8 :8, + fagc_ref_h_eqst9 :8, + reserved79 :16; +}; +union ATSC_DEMOD_REG_0X88_BITS { + unsigned int bits; + struct{ + unsigned int ccfo_pow_peak :16, + ccfo_avg_peak :16; + } b; +}; + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq.h new file mode 100644 index 0000000..2cc1348 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq.h @@ -0,0 +1,98 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_eq.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_EQ_H__ +#define __ADDR_ATSC_EQ_H__ +#include "addr_atsc_eq_bit.h" + +#define MOD_ATSC_EQ 0x0 +#define ATSC_EQ_ADDR(x) (MOD_ATSC_EQ+(x)) + +#define ATSC_EQ_REG_0X90 ATSC_EQ_ADDR(0x90) +#define ATSC_EQ_REG_0X91 ATSC_EQ_ADDR(0x91) +#define ATSC_EQ_REG_0X92 ATSC_EQ_ADDR(0x92) +#define ATSC_EQ_REG_0X93 ATSC_EQ_ADDR(0x93) +#define ATSC_EQ_REG_0X94 ATSC_EQ_ADDR(0x94) +#define ATSC_EQ_REG_0X95 ATSC_EQ_ADDR(0x95) +#define ATSC_EQ_REG_0X96 ATSC_EQ_ADDR(0x96) +#define ATSC_EQ_REG_0X97 ATSC_EQ_ADDR(0x97) +#define ATSC_EQ_REG_0X98 ATSC_EQ_ADDR(0x98) +#define ATSC_EQ_REG_0X99 ATSC_EQ_ADDR(0x99) +#define ATSC_EQ_REG_0X9A ATSC_EQ_ADDR(0x9a) +#define ATSC_EQ_REG_0X9B ATSC_EQ_ADDR(0x9b) +#define ATSC_EQ_REG_0X9C ATSC_EQ_ADDR(0x9c) +#define ATSC_EQ_REG_0X9D ATSC_EQ_ADDR(0x9d) +#define ATSC_EQ_REG_0X9E ATSC_EQ_ADDR(0x9e) +#define ATSC_EQ_REG_0X9F ATSC_EQ_ADDR(0x9f) +#define ATSC_EQ_REG_0XA0 ATSC_EQ_ADDR(0xa0) +#define ATSC_EQ_REG_0XA1 ATSC_EQ_ADDR(0xa1) +#define ATSC_EQ_REG_0XA2 ATSC_EQ_ADDR(0xa2) +#define ATSC_EQ_REG_0XA3 ATSC_EQ_ADDR(0xa3) +#define ATSC_EQ_REG_0XA4 ATSC_EQ_ADDR(0xa4) +#define ATSC_EQ_REG_0XA5 ATSC_EQ_ADDR(0xa5) +#define ATSC_EQ_REG_0XA6 ATSC_EQ_ADDR(0xa6) +#define ATSC_EQ_REG_0XA7 ATSC_EQ_ADDR(0xa7) +#define ATSC_EQ_REG_0XA8 ATSC_EQ_ADDR(0xa8) +#define ATSC_EQ_REG_0XA9 ATSC_EQ_ADDR(0xa9) +#define ATSC_EQ_REG_0XAA ATSC_EQ_ADDR(0xaa) +#define ATSC_EQ_REG_0XAB ATSC_EQ_ADDR(0xab) +#define ATSC_EQ_REG_0XAC ATSC_EQ_ADDR(0xac) +#define ATSC_EQ_REG_0XAD ATSC_EQ_ADDR(0xad) +#define ATSC_EQ_REG_0XAE ATSC_EQ_ADDR(0xae) +#define ATSC_EQ_REG_0XAF ATSC_EQ_ADDR(0xaf) +#define ATSC_EQ_REG_0XB0 ATSC_EQ_ADDR(0xb0) +#define ATSC_EQ_REG_0XB1 ATSC_EQ_ADDR(0xb1) +#define ATSC_EQ_REG_0XB2 ATSC_EQ_ADDR(0xb2) +#define ATSC_EQ_REG_0XB3 ATSC_EQ_ADDR(0xb3) +#define ATSC_EQ_REG_0XB4 ATSC_EQ_ADDR(0xb4) +#define ATSC_EQ_REG_0XB5 ATSC_EQ_ADDR(0xb5) +#define ATSC_EQ_REG_0XB6 ATSC_EQ_ADDR(0xb6) +#define ATSC_EQ_REG_0XB7 ATSC_EQ_ADDR(0xb7) +#define ATSC_EQ_REG_0XB8 ATSC_EQ_ADDR(0xb8) +#define ATSC_EQ_REG_0XB9 ATSC_EQ_ADDR(0xb9) +#define ATSC_EQ_REG_0XBA ATSC_EQ_ADDR(0xba) +#define ATSC_EQ_REG_0XBB ATSC_EQ_ADDR(0xbb) +#define ATSC_EQ_REG_0XBC ATSC_EQ_ADDR(0xbc) +#define ATSC_EQ_REG_0XBD ATSC_EQ_ADDR(0xbd) +#define ATSC_EQ_REG_0XBE ATSC_EQ_ADDR(0xbe) +#define ATSC_EQ_REG_0XBF ATSC_EQ_ADDR(0xbf) +#define ATSC_EQ_REG_0XC0 ATSC_EQ_ADDR(0xc0) +#define ATSC_EQ_REG_0XC1 ATSC_EQ_ADDR(0xc1) +#define ATSC_EQ_REG_0XC2 ATSC_EQ_ADDR(0xc2) +#define ATSC_EQ_REG_0XC3 ATSC_EQ_ADDR(0xc3) +#define ATSC_EQ_REG_0XC4 ATSC_EQ_ADDR(0xc4) +#define ATSC_EQ_REG_0XC5 ATSC_EQ_ADDR(0xc5) +#define ATSC_EQ_REG_0XC6 ATSC_EQ_ADDR(0xc6) +#define ATSC_EQ_REG_0XC7 ATSC_EQ_ADDR(0xc7) +#define ATSC_EQ_REG_0XC8 ATSC_EQ_ADDR(0xc8) +#define ATSC_EQ_REG_0XC9 ATSC_EQ_ADDR(0xc9) +#define ATSC_EQ_REG_0XCA ATSC_EQ_ADDR(0xca) +#define ATSC_EQ_REG_0XCB ATSC_EQ_ADDR(0xcb) +#define ATSC_EQ_REG_0XCC ATSC_EQ_ADDR(0xcc) +#define ATSC_EQ_REG_0XCD ATSC_EQ_ADDR(0xcd) +#define ATSC_EQ_REG_0XD0 ATSC_EQ_ADDR(0xd0) +#define ATSC_EQ_REG_0XD1 ATSC_EQ_ADDR(0xd1) +#define ATSC_EQ_REG_0XD2 ATSC_EQ_ADDR(0xd2) +#define ATSC_EQ_REG_0XD3 ATSC_EQ_ADDR(0xd3) +#define ATSC_EQ_REG_0XD4 ATSC_EQ_ADDR(0xd4) +#define ATSC_EQ_REG_0XD5 ATSC_EQ_ADDR(0xd5) +#define ATSC_EQ_REG_0XD6 ATSC_EQ_ADDR(0xd6) +#define ATSC_EQ_REG_0XD7 ATSC_EQ_ADDR(0xd7) +#define ATSC_EQ_REG_0XD8 ATSC_EQ_ADDR(0xd8) +#define ATSC_EQ_REG_0XD9 ATSC_EQ_ADDR(0xd9) + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq_bit.h b/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq_bit.h new file mode 100644 index 0000000..4714ef49 --- /dev/null +++ b/drivers/amlogic/media/dtv_demod/include/addr_atsc_eq_bit.h @@ -0,0 +1,516 @@ +/* + * drivers/amlogic/media/dtv_demod/include/addr_atsc_eq_bit.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __ADDR_ATSC_EQ_BIT_H__ +#define __ADDR_ATSC_EQ_BIT_H__ + +struct ATSC_EQ_REG_0X90_BITS { + unsigned int eq_sm_ow_ctrl :10, + reserved0 :22; +}; +union ATSC_EQ_REG_0X91_BITS { + unsigned int bits; + struct { + unsigned int pn63_err_gen_en :1, + reserved1 :3, + ffe_out_sft_left_one :1, + reserved2 :3, + fft_leak_type_sel :1, + reserved3 :3, + iir_limit_sel :1, + reserved4 :3, + iir_tap_rw_en :1, + reserved5 :3, + div_path_sel :1, + reserved6 :3, + div_en :1, + reserved7 :3, + dfe_tap_wr_en :1, + reserved8 :3; + } b; +}; +union ATSC_EQ_REG_0X92_BITS { + unsigned int bits; + struct { + unsigned int dec_stage_sel :4, + nco_trk_phs_rnd :4, + eq_ph_loop_open :8, + dfe_dly_sym_slicer_sel :3, + reserved9 :1, + err_gen_sel :2, + reserved10 :2, + eq_err_rot_en :1, + reserved11 :5, + cwrmv_enable :1, + reserved12 :1; + } b; +}; + +union ATSC_EQ_REG_0X93_BITS { + unsigned int bits; + struct { + unsigned int eq_out_start_dly :11, + reserved13 :5, + eq_ffe_symb_thr :8, + fir_out_exp :5, + reserved14 :3; + } b; +}; +struct ATSC_EQ_REG_0X94_BITS { + unsigned int snr_calc_num :16, + err_fft_start_cnt :16; +}; + +struct ATSC_EQ_REG_0X95_BITS { + unsigned int stswthup1 :8, + stswthup2 :8, + stswthup3 :8, + stswthup4 :8; +}; +struct ATSC_EQ_REG_0X96_BITS { + unsigned int stswthup5 :8, + stswthup6 :8, + stswthup7 :8, + stswthup8 :8; +}; +struct ATSC_EQ_REG_0X97_BITS { + unsigned int stswthdn1 :8, + stswthdn2 :8, + stswthdn3 :8, + stswthdn4 :8; +}; +struct ATSC_EQ_REG_0X98_BITS { + unsigned int stswthdn5 :8, + stswthdn6 :8, + stswthdn7 :8, + stswthdn8 :8; +}; +struct ATSC_EQ_REG_0X99_BITS { + unsigned int fir_step_1t :5, + reserved15 :3, + fir_step_2t :5, + reserved16 :3, + fir_step_3t :5, + reserved17 :3, + fir_step_4t :5, + reserved18 :3; +}; +struct ATSC_EQ_REG_0X9A_BITS { + unsigned int fir_step_5t :5, + reserved19 :3, + fir_step_6t :5, + reserved20 :3, + fir_step_7t :5, + reserved21 :3, + fir_step_8t :5, + reserved22 :3; +}; +struct ATSC_EQ_REG_0X9B_BITS { + unsigned int fir_step_1d :5, + reserved23 :3, + fir_step_2d :5, + reserved24 :3, + fir_step_3d :5, + reserved25 :3, + fir_step_4d :5, + reserved26 :3; +}; +struct ATSC_EQ_REG_0X9C_BITS { + unsigned int fir_step_5d :5, + reserved27 :3, + fir_step_6d :5, + reserved28 :3, + fir_step_7d :5, + reserved29 :3, + fir_step_8d :5, + reserved30 :3; +}; +struct ATSC_EQ_REG_0X9D_BITS { + unsigned int step_size_exp5_1 :5, + reserved31 :3, + step_size_exp5_2 :5, + reserved32 :3, + step_size_exp5_3 :5, + reserved33 :3, + step_size_exp5_4 :5, + reserved34 :3; +}; +struct ATSC_EQ_REG_0X9E_BITS { + unsigned int step_size_exp5_5 :5, + reserved35 :3, + step_size_exp5_6 :5, + reserved36 :3, + step_size_exp5_7 :5, + reserved37 :3, + step_size_exp5_8 :5, + reserved38 :3; +}; +struct ATSC_EQ_REG_0X9F_BITS { + unsigned int iir_gn4 :7, + reserved39 :1, + iir_gn5 :7, + reserved40 :1, + iir_gn6 :7, + reserved41 :1, + iir_gn7 :7, + reserved42 :1; +}; +struct ATSC_EQ_REG_0XA0_BITS { + unsigned int iir_gn8 :7, + reserved43 :25; +}; +struct ATSC_EQ_REG_0XA1_BITS { + unsigned int iir_gn4t :7, + reserved44 :1, + iir_gn5t :7, + reserved45 :1, + iir_gn6t :7, + reserved46 :1, + iir_gn7t :7, + reserved47 :1; +}; +struct ATSC_EQ_REG_0XA2_BITS { + unsigned int iir_gn8t :7, + reserved48 :25; +}; +struct ATSC_EQ_REG_0XA3_BITS { + unsigned int ft_step_size5 :4, + ft_step_size6 :4, + ft_step_size7 :4, + ft_step_size8 :4, + pt_step_size5 :4, + pt_step_size6 :4, + pt_step_size7 :4, + pt_step_size8 :4; +}; +struct ATSC_EQ_REG_0XA4_BITS { + unsigned int pt_gain_size5 :5, + reserved49 :3, + pt_gain_size6 :5, + reserved50 :3, + pt_gain_size7 :5, + reserved51 :3, + pt_gain_size8 :5, + reserved52 :3; +}; +union ATSC_EQ_REG_0XA5_BITS { + unsigned int bits; + struct{ + unsigned int eqst2_up_cnt :8, + eqst3_up_cnt :8, + eqst4_up_cnt :8, + eqst5_up_cnt :8; + } b; +}; +struct ATSC_EQ_REG_0XA6_BITS { + unsigned int eqst6_up_cnt :8, + eqst7_up_cnt :8, + eqst8_up_cnt :8, + eqst9_up_cnt :8; +}; +struct ATSC_EQ_REG_0XA7_BITS { + unsigned int eqst2_to_cnt :7, + reserved53 :1, + eqst3_to_cnt :7, + reserved54 :1, + eqst4_to_cnt :7, + reserved55 :1, + eqst5_to_cnt :7, + reserved56 :1; +}; +struct ATSC_EQ_REG_0XA8_BITS { + unsigned int eqst6_to_cnt :7, + reserved57 :1, + eqst7_to_cnt :7, + reserved58 :1, + eqst8_to_cnt :7, + reserved59 :1, + eqst9_to_cnt :7, + reserved60 :1; +}; +union ATSC_EQ_REG_0XA9_BITS { + unsigned int bits; + struct{ + unsigned int iir_err_range_sel4 :3, + reserved61 :1, + iir_err_range_sel5 :3, + reserved62 :1, + iir_err_range_sel6 :3, + reserved63 :1, + iir_err_range_sel7 :3, + reserved64 :1, + iir_err_range_sel8 :3, + reserved65 :13; + } b; +}; +struct ATSC_EQ_REG_0XAA_BITS { + unsigned int eq_ctrl0 :10, + reserved66 :6, + eq_ctrl1 :10, + reserved67 :6; +}; +struct ATSC_EQ_REG_0XAB_BITS { + unsigned int eq_ctrl2 :10, + reserved68 :6, + eq_ctrl3 :10, + reserved69 :6; +}; +struct ATSC_EQ_REG_0XAC_BITS { + unsigned int eq_ctrl4 :10, + reserved70 :6, + eq_ctrl5 :10, + reserved71 :6; +}; +union ATSC_EQ_REG_0XAD_BITS { + unsigned int bits; + struct { + unsigned int eq_ctrl6 :10, + reserved72 :6, + eq_ctrl7 :10, + reserved73 :6; + } b; +}; +struct ATSC_EQ_REG_0XAE_BITS { + unsigned int eq_ctrl8 :10, + reserved74 :6, + eq_ctrl9 :10, + reserved75 :6; +}; +struct ATSC_EQ_REG_0XAF_BITS { + unsigned int ffe_leak_set_rca1 :12, + reserved76 :4, + ffe_leak_set_train :12, + reserved77 :4; +}; +struct ATSC_EQ_REG_0XB0_BITS { + unsigned int ffe_leak_set_ddm :12, + reserved78 :4, + ffe_leak_set_rca2 :12, + reserved79 :4; +}; +struct ATSC_EQ_REG_0XB1_BITS { + unsigned int ffe_slope_leak_set_rca1 :12, + reserved80 :4, + ffe_slope_leak_set_train :12, + reserved81 :4; +}; +struct ATSC_EQ_REG_0XB2_BITS { + unsigned int ffe_slope_leak_set_ddm :12, + reserved82 :4, + ffe_slope_leak_set_rca2 :12, + reserved83 :4; +}; +struct ATSC_EQ_REG_0XB3_BITS { + unsigned int ffe_leak_rate_set_ddm :8, + ffe_leak_rate_set_rca2 :8, + ffe_leak_rate_set_rca1 :8, + ffe_leak_rate_set_train :8; +}; +struct ATSC_EQ_REG_0XB4_BITS { + unsigned int err_limit_set_ddm_rca :4, + err_limit_set_rca2_rca :4, + err_limit_set_rca1_rca :4, + err_limit_set_train_rca :4, + err_limit_set_ddm_cma :4, + err_limit_set_rca2_cma :4, + err_limit_set_rca1_cma :4, + err_limit_set_train_cma :4; +}; +struct ATSC_EQ_REG_0XB5_BITS { + unsigned int ffe_tap_update_limit_set_ddm :4, + ffe_tap_update_limit_set_rca2 :4, + ffe_tap_update_limit_set_rca1 :4, + ffe_tap_update_limit_set_train :4, + ffe_stepsizexerr_limit_set_ddm :4, + ffe_stepsizexerr_limit_set_rca2 :4, + ffe_stepsizexerr_limit_set_rca1 :4, + ffe_stepsizexerr_limit_set_train :4; +}; +struct ATSC_EQ_REG_0XB6_BITS { + unsigned int ffe_conj_data_limit_set_ddm :5, + reserved84 :3, + ffe_conj_data_limit_set_rca2 :5, + reserved85 :3, + ffe_conj_data_limit_set_rca1 :5, + reserved86 :3, + ffe_conj_data_limit_set_train :5, + reserved87 :3; +}; +struct ATSC_EQ_REG_0XB7_BITS { + unsigned int iir_leak_rate_ddm :16, + iir_leak_rate_blind :16; +}; +struct ATSC_EQ_REG_0XB8_BITS { + unsigned int iir_leak_rate1_ddm :16, + iir_leak_rate1_blind :16; +}; +struct ATSC_EQ_REG_0XB9_BITS { + unsigned int iir1_st0_tap_limit_up4 :8, + iir1_st0_tap_limit_up5 :8, + iir1_st0_tap_limit_up6 :8, + iir1_st0_tap_limit_up7 :8; +}; +struct ATSC_EQ_REG_0XBA_BITS { + unsigned int iir1_st0_tap_limit_up8 :8, + iir1_st0_tap_limit_low4 :8, + iir1_st0_tap_limit_low5 :8, + iir1_st0_tap_limit_low6 :8; +}; +struct ATSC_EQ_REG_0XBB_BITS { + unsigned int iir1_st0_tap_limit_low7 :8, + iir1_st0_tap_limit_low8 :8, + iir1_st1_tap_limit_up4 :8, + iir1_st1_tap_limit_up5 :8; +}; +struct ATSC_EQ_REG_0XBC_BITS { + unsigned int iir1_st1_tap_limit_up6 :8, + iir1_st1_tap_limit_up7 :8, + iir1_st1_tap_limit_up8 :8, + iir1_st1_tap_limit_low4 :8; +}; +struct ATSC_EQ_REG_0XBD_BITS { + unsigned int iir1_st1_tap_limit_low5 :8, + iir1_st1_tap_limit_low6 :8, + iir1_st1_tap_limit_low7 :8, + iir1_st1_tap_limit_low8 :8; +}; +struct ATSC_EQ_REG_0XBE_BITS { + unsigned int iir2_st0_tap_limit_up4 :8, + iir2_st0_tap_limit_up5 :8, + iir2_st0_tap_limit_up6 :8, + iir2_st0_tap_limit_up7 :8; +}; +struct ATSC_EQ_REG_0XBF_BITS { + unsigned int iir2_st0_tap_limit_up8 :8, + iir2_st0_tap_limit_low4 :8, + iir2_st0_tap_limit_low5 :8, + iir2_st0_tap_limit_low6 :8; +}; +struct ATSC_EQ_REG_0XC0_BITS { + unsigned int iir2_st0_tap_limit_low7 :8, + iir2_st0_tap_limit_low8 :8, + reserved88 :16; +}; +struct ATSC_EQ_REG_0XC1_BITS { + unsigned int bm_acum_min_diff_ctrl :24, + reserved89 :8; +}; +struct ATSC_EQ_REG_0XC2_BITS { + unsigned int pt_err_limit :16, + reserved90 :16; +}; +struct ATSC_EQ_REG_0XC3_BITS { + unsigned int snr :16, + reserved91 :16; +}; +struct ATSC_EQ_REG_0XC4_BITS { + unsigned int bm_acum_diff :21, + reserved92 :11; +}; +struct ATSC_EQ_REG_0XC5_BITS { + unsigned int cwth_exp :10, + reserved93 :6, + pwr_avgw :8, + reserved94 :8; +}; +struct ATSC_EQ_REG_0XC6_BITS { + unsigned int cwth_man :24, + reserved95 :8; +}; +struct ATSC_EQ_REG_0XC7_BITS { + unsigned int inband_pwr_th :16, + reserved96 :16; +}; +union ATSC_EQ_REG_0XC8_BITS { + unsigned int bits; + struct { + unsigned int timing_adjust_thd :16, + timing_adjust_eqst :2, + reserved97 :6, + timing_adjust_bypass :1, + reserved98 :7; + } b; +}; +struct ATSC_EQ_REG_0XC9_BITS { + unsigned int timing_adjust_snr_thd :16, + timing_adjust_thd_1 :16; +}; +union ATSC_EQ_REG_0XCA_BITS { + unsigned int bits; + struct { + unsigned int timing_offset :9, + reserved99 :7, + timing_direct :1, + reserved100 :15; + } b; +}; +struct ATSC_EQ_REG_0XCB_BITS { + unsigned int timing_adjust_sum :22, + reserved101 :10; +}; +struct ATSC_EQ_REG_0XCC_BITS { + unsigned int timing_adjust_max :22, + reserved102 :10; +}; +struct ATSC_EQ_REG_0XCD_BITS { + unsigned int timing_adjust_ori :22, + reserved103 :10; +}; +struct ATSC_EQ_REG_0XD0_BITS { + unsigned int tap_fd_step1 :8, + tap_fd_ctrl :8, + ar_stop_st :4, + reserved104 :12; +}; +struct ATSC_EQ_REG_0XD2_BITS { + unsigned int tap_shift_ctrl0 :8, + tap_shift_ctrl1 :8, + tap_shift_ctrl2 :8, + tap_shift_ctrl3 :8; +}; +struct ATSC_EQ_REG_0XD3_BITS { + unsigned int tap_shift_ctrl4 :8, + tap_shift_ctrl5 :8, + tap_shift_ctrl6 :8, + tap_shift_ctrl7 :8; +}; +struct ATSC_EQ_REG_0XD4_BITS { + unsigned int tap_shift_ctrl8 :8, + tap_shift_ctrl9 :8, + tap_shift_ctrla :8, + tap_shift_ctrlb :8; +}; +struct ATSC_EQ_REG_0XD5_BITS { + unsigned int tap_shift_ctrlc :8, + tap_shift_ctrld :8, + tap_shift_ctrle :8, + tap_shift_ctrlf :8; +}; +struct ATSC_EQ_REG_0XD6_BITS { + unsigned int tap_mask_adr :16, + reserved105 :16; +}; +struct ATSC_EQ_REG_0XD7_BITS { + unsigned int tap_dfe_abs :21, + reserved106 :11; +}; +struct ATSC_EQ_REG_0XD9_BITS { + unsigned int tap_snr :16, + reserved107 :16; +}; + +#endif diff --git a/drivers/amlogic/media/dtv_demod/include/amlfrontend.h b/drivers/amlogic/media/dtv_demod/include/amlfrontend.h index e570885..ab220b2 100644 --- a/drivers/amlogic/media/dtv_demod/include/amlfrontend.h +++ b/drivers/amlogic/media/dtv_demod/include/amlfrontend.h @@ -60,6 +60,7 @@ enum Gxtv_Demod_Dvb_Mode { #define Demod_Clk_180M 180000 /* */ #define Demod_Clk_200M 200000 /* */ #define Demod_Clk_225M 225000 +#define Demod_Clk_250M 250000 #define Adc_Clk_27M 27777 /* atsc */ #define Demod_Clk_83M 83333 /* */ @@ -93,7 +94,8 @@ struct ss_reg_vt { /* rigister offset page */ #define IC_OFFS_V2 (0x02) /*MG9TV, GXTVBB, TXL*/ -#define IC_OFFS_V3 (0x03) /*TXLX, GXLX...*/ +#define IC_OFFS_V3 (0x03) /*TXLX, GXLX, TXHD*/ +#define IC_OFFS_V4 (0x04) /*TL1*/ @@ -108,17 +110,15 @@ struct ss_reg_vt { #define IC_DVBT_V2 (0x02) /*TXLX*/ #define IC_ATSC_V2 (0x02) /*TXLX*/ -#define IC_OFFS_V2 (0x02) /*MG9TV, GXTVBB, TXL*/ -#define IC_OFFS_V3 (0x03) /*TXLX, GXLX, TXHD*/ - /*-----------------------*/ #define IC_VER_GTVBB (0x00) #define IC_VER_TXL (0x01) #define IC_VER_TXLX (0x02) #define IC_VER_GXLX (0x03) #define IC_VER_TXHD (0x04) +#define IC_VER_TL1 (0x05) -#define IC_VER_NUB (0x05) +#define IC_VER_NUB (0x06) /*-----------------------*/ @@ -154,11 +154,13 @@ struct ic_ver { }; struct ddemod_reg_off { /* register address offset for demod*/ - unsigned int off_demod; + unsigned int off_demod_top; unsigned int off_dvbc; unsigned int off_dtmb; unsigned int off_dvbt; unsigned int off_atsc; + unsigned int off_front; + unsigned int off_isdbt; #if 0 /*vertual address for dtv demod*/ @@ -263,7 +265,7 @@ struct amldtvdemod_device_s { struct dvb_frontend frontend; /**/ #endif const struct amlfe_exp_config *afe_cfg; - + struct dentry *demod_root; }; extern struct amldtvdemod_device_s *dtvdd_devp; /**/ @@ -393,7 +395,19 @@ static inline void __iomem *gbase_atsc(void) static inline void __iomem *gbase_demod(void) { return dtvdd_devp->reg_v[ES_MAP_ADDR_DEMOD].v - + dtvdd_devp->ireg.off_demod; + + dtvdd_devp->ireg.off_demod_top; +} + +static inline void __iomem *gbase_isdbt(void) +{ + return dtvdd_devp->reg_v[ES_MAP_ADDR_DEMOD].v + + dtvdd_devp->ireg.off_isdbt; +} + +static inline void __iomem *gbase_front(void) +{ + return dtvdd_devp->reg_v[ES_MAP_ADDR_DEMOD].v + + dtvdd_devp->ireg.off_front; } static inline void __iomem *gbase_aobus(void) @@ -417,7 +431,7 @@ static inline unsigned int gphybase_demod(void) static inline unsigned int gphybase_demodcfg(void) { return dtvdd_devp->reg_p[ES_MAP_ADDR_DEMOD].phy_addr - + dtvdd_devp->ireg.off_demod; + + dtvdd_devp->ireg.off_demod_top; } static inline unsigned int gphybase_hiu(void) diff --git a/drivers/amlogic/media/dtv_demod/include/atsc_func.h b/drivers/amlogic/media/dtv_demod/include/atsc_func.h index 77b10c5..5ead9ab 100644 --- a/drivers/amlogic/media/dtv_demod/include/atsc_func.h +++ b/drivers/amlogic/media/dtv_demod/include/atsc_func.h @@ -53,6 +53,8 @@ int check_atsc_fsm_status(void); void atsc_write_reg(unsigned int reg_addr, unsigned int reg_data); unsigned int atsc_read_reg(unsigned int reg_addr); +extern void atsc_write_reg_v4(unsigned int addr, unsigned int data); +extern unsigned int atsc_read_reg_v4(unsigned int addr); unsigned int atsc_read_iqr_reg(void); diff --git a/drivers/amlogic/media/dtv_demod/include/demod_func.h b/drivers/amlogic/media/dtv_demod/include/demod_func.h index 9be8d2e..79f9554 100644 --- a/drivers/amlogic/media/dtv_demod/include/demod_func.h +++ b/drivers/amlogic/media/dtv_demod/include/demod_func.h @@ -26,6 +26,10 @@ #include "dvb_frontend.h" /**/ #include "amlfrontend.h" #include "addr_dtmb_top.h" +#include "addr_atsc_demod.h" +#include "addr_atsc_eq.h" +#include "addr_atsc_cntr.h" + /*#include "c_stb_define.h"*/ /*#include "c_stb_regs_define.h"*/ #include @@ -117,10 +121,13 @@ /* demod register */ -#define DEMOD_REG1 (0x00) -#define DEMOD_REG2 (0x04) -#define DEMOD_REG3 (0x08) -#define DEMOD_REG4 (0x0C) +#define DEMOD_TOP_REG0 (0x00) +#define DEMOD_TOP_REG4 (0x04) +#define DEMOD_TOP_REG8 (0x08) +#define DEMOD_TOP_REGC (0x0C) + +/*reset register*/ +#define reg_reset (0x1c) #if 0 /* demod register: */ @@ -254,9 +261,9 @@ #define ADC_REG6 0x1074 #endif -#define DEMOD_REG1_VALUE 0x0000d007 -#define DEMOD_REG2_VALUE 0x2e805400 -#define DEMOD_REG3_VALUE 0x201 +#define DEMOD_REG0_VALUE 0x0000d007 +#define DEMOD_REG4_VALUE 0x2e805400 +#define DEMOD_REG8_VALUE 0x201 /* for table end */ #define TABLE_FLG_END 0xffffffff @@ -548,6 +555,7 @@ int app_apb_read_reg(int addr); void demod_set_cbus_reg(unsigned int data, unsigned int addr); unsigned int demod_read_cbus_reg(unsigned int addr); void demod_set_demod_reg(unsigned int data, unsigned int addr); +extern void demod_set_tvfe_reg(unsigned int data, unsigned int addr); unsigned int demod_read_demod_reg(unsigned int addr); /* extern int clk_measure(char index); */ @@ -571,6 +579,9 @@ void demod_get_reg(struct aml_demod_reg *demod_reg); int demod_set_sys(struct aml_demod_sta *demod_sta, /*struct aml_demod_i2c *demod_i2c,*/ struct aml_demod_sys *demod_sys); +extern void demod_set_sys_dtmb_v4(void); +extern void demod_set_sys_atsc_v4(void); +extern void set_j83b_filter_reg_v4(void); /* for g9tv */ @@ -799,9 +810,15 @@ extern unsigned int demod_read_reg_rlt(unsigned int addr); #endif extern void dvbc_write_reg(unsigned int addr, unsigned int data); extern unsigned int dvbc_read_reg(unsigned int addr); +extern void dvbc_write_reg_v4(unsigned int addr, unsigned int data); +extern unsigned int dvbc_read_reg_v4(unsigned int addr); extern void demod_write_reg(unsigned int addr, unsigned int data); extern unsigned int demod_read_reg(unsigned int addr); - +//extern void demod_init_mutex(void); +extern void front_write_reg_v4(unsigned int addr, unsigned int data); +extern unsigned int front_read_reg_v4(unsigned int addr); +extern unsigned int isdbt_read_reg_v4(unsigned int addr); +extern void isdbt_write_reg_v4(unsigned int addr, unsigned int data); extern int dd_tvafe_hiu_reg_write(unsigned int reg, unsigned int val); extern unsigned int dd_tvafe_hiu_reg_read(unsigned int addr); diff --git a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c index d35b2e0..a6e80fc 100644 --- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c +++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c @@ -550,6 +550,17 @@ void tvafe_set_ddemod_default(void) W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710); W_APB_REG(TVFE_VAFE_CTRL1, 0x0); W_APB_REG(TVFE_VAFE_CTRL2, 0x1010eeb0); + } else if (tvafe_cpu_type() == CPU_TYPE_TL1) { + W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710); + W_APB_REG(TVFE_VAFE_CTRL1, 0x3000); + W_APB_REG(TVFE_VAFE_CTRL2, 0x1fe09e31); + + W_HIU_REG(HHI_DADC_CNTL, 0x0030303c); + W_HIU_REG(HHI_DADC_CNTL2, 0x00003480); + W_HIU_REG(HHI_DADC_CNTL3, 0x08300b83); + + //HHI_VDAC_CNTL1 + W_HIU_REG(0xbc, 0x0); } } @@ -775,7 +786,7 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara) W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0); W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0); W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x05400000); - W_HIU_REG(HHI_ADC_PLL_CNTL2_TL1, 0xe1800000); + W_HIU_REG(HHI_ADC_PLL_CNTL2_TL1, 0xe0800000); W_HIU_REG(HHI_ADC_PLL_CNTL3_TL1, 0x48681c00); W_HIU_REG(HHI_ADC_PLL_CNTL4_TL1, 0x88770290); W_HIU_REG(HHI_ADC_PLL_CNTL5_TL1, 0x39272000); @@ -786,6 +797,11 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara) adc_pll_lock_cnt++; } while (!R_HIU_BIT(HHI_ADC_PLL_CNTL0_TL1, 31, 1) && (adc_pll_lock_cnt < 10)); + + W_HIU_REG(0xf3, 0x00800000); + //HHI_AUDPLL_CLK_OUT_CNTL + W_HIU_REG(0x74, 0x501); + } else if (tvafe_cpu_type() == CPU_TYPE_TXL || tvafe_cpu_type() == CPU_TYPE_TXLX || tvafe_cpu_type() == CPU_TYPE_TXHD) { diff --git a/include/uapi/linux/dvb/aml_demod.h b/include/uapi/linux/dvb/aml_demod.h index 342e690..3738e5e 100644 --- a/include/uapi/linux/dvb/aml_demod.h +++ b/include/uapi/linux/dvb/aml_demod.h @@ -176,6 +176,20 @@ struct aml_demod_para { u32_t dtmb_coderate; }; +//cmd +#define AML_DBG_DEMOD_TOP_RW 0 +#define AML_DBG_DVBC_RW 1 +#define AML_DBG_ATSC_RW 2 +#define AML_DBG_DTMB_RW 3 +#define AML_DBG_FRONT_RW 4 +#define AML_DBG_ISDBT_RW 5 +#define AML_DBG_DVBC_INIT 6 +#define AML_DBG_ATSC_INIT 7 +#define AML_DBG_DTMB_INIT 8 +#define AML_DBG_DEMOD_SYMB_RATE 9 +#define AML_DBG_DEMOD_CH_FREQ 10 +#define AML_DBG_DEMOD_MODUL 11 + #define AML_DEMOD_SET_SYS _IOW('D', 0, struct aml_demod_sys) #define AML_DEMOD_GET_SYS _IOR('D', 1, struct aml_demod_sys) @@ -219,5 +233,17 @@ int read_memory_to_file(struct aml_cap_data *cap); int read_reg(int addr); void wait_capture(int cap_cur_addr, int depth_MB, int start); int cap_adc_data(struct aml_cap_data *cap); +extern unsigned int get_symbol_rate(void); +extern unsigned int get_ch_freq(void); +extern unsigned int get_modu(void); +extern void demod_set_sys_dtmb_v4(void); +extern void tuner_set_atsc_para(void); +extern void tuner_set_dtmb_para(void); +extern void tuner_set_qam_para(void); +extern void tuner_config_atsc(void); +extern void attach_tuner_demod(void); +extern void tuner_set_freq(unsigned int freq); +extern void tuner_config_dtmb(void); +extern void tuner_config_qam(void); #endif /* AML_DEMOD_H */ -- 2.7.4