From 196de71a9d9e9090406a87362d22b67ae633fa7a Mon Sep 17 00:00:00 2001 From: James Liao Date: Fri, 10 Jul 2015 16:39:33 +0800 Subject: [PATCH] clk: mediatek: Fix calculation of PLL rate settings Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao Acked-by: Sascha Hauer Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 68af518..0e3f4ef 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, if (freq > pll->data->fmax) freq = pll->data->fmax; - for (val = 0; val < 4; val++) { + for (val = 0; val < 5; val++) { *postdiv = 1 << val; - if (freq * *postdiv >= fmin) + if ((u64)freq * *postdiv >= fmin) break; } -- 2.7.4