From 18b542e544d3bd00e55d7135ee673b34dbfdb9b9 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Fri, 2 Dec 2022 12:52:16 +0100 Subject: [PATCH] arm64: dts: Add DT node for the VIPNano-QI on the A311D This "NPU" is very similar to the Vivante GPUs and Etnaviv works well with it with just a few small changes. v2: Add reference to RESET_NNA (Neil) v3: Fix indentation (Neil) Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20221202115223.39051-5-tomeu.vizoso@collabora.com [narmstrong: squash patch 8, disable NPU by default and do not enable NPU on vim3 yet] Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 10 ++++++++++ arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 9dbd508..585dd70 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2490,4 +2490,14 @@ #clock-cells = <0>; }; + npu: npu@ff100000 { + compatible = "vivante,gc"; + reg = <0x0 0xff100000 0x0 0x20000>; + interrupts = <0 147 4>; + clocks = <&clkc CLKID_NNA_CORE_CLK>, + <&clkc CLKID_NNA_AXI_CLK>; + clock-names = "core", "bus"; + resets = <&reset RESET_NNA>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 75ff00f..431572b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -144,3 +144,7 @@ &pmu { compatible = "amlogic,g12b-ddr-pmu"; }; + +&npu { + power-domains = <&pwrc PWRC_G12A_NNA_ID>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 56ca0ba..617d322 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -548,3 +548,7 @@ &usb { power-domains = <&pwrc PWRC_SM1_USB_ID>; }; + +&npu { + power-domains = <&pwrc PWRC_SM1_NNA_ID>; +}; -- 2.7.4