From 1884ada741c90602a7dfa33867c68cd290838241 Mon Sep 17 00:00:00 2001
From: Nicola Lancellotti <nicola.lancellotti@arm.com>
Date: Tue, 22 Nov 2022 15:25:13 +0000
Subject: [PATCH] [AArch64] Pre-commit test for "Add patterns for SVE
 predicated add/sub and mov combine"

---
 llvm/test/CodeGen/AArch64/predicated-add-sub.ll | 466 ++++++++++++++++++++++++
 1 file changed, 466 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/predicated-add-sub.ll

diff --git a/llvm/test/CodeGen/AArch64/predicated-add-sub.ll b/llvm/test/CodeGen/AArch64/predicated-add-sub.ll
new file mode 100644
index 0000000..9a778fb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/predicated-add-sub.ll
@@ -0,0 +1,466 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux"
+
+define <vscale x 8 x i8> @zext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.8xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  %result = add <vscale x 8 x i8> %a, %extend
+  ret <vscale x 8 x i8> %result
+}
+
+define <vscale x 4 x i16> @zext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.4xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  %result = add <vscale x 4 x i16> %a, %extend
+  ret <vscale x 4 x i16> %result
+}
+
+define <vscale x 2 x i32> @zext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.2xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  %result = add <vscale x 2 x i32> %a, %extend
+  ret <vscale x 2 x i32> %result
+}
+
+define <vscale x 16 x i8> @zext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.16xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.b, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  %result = add <vscale x 16 x i8> %a, %extend
+  ret <vscale x 16 x i8> %result
+}
+
+define <vscale x 8 x i16> @zext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.8xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  %result = add <vscale x 8 x i16> %a, %extend
+  ret <vscale x 8 x i16> %result
+}
+
+define <vscale x 4 x i32> @zext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.4xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  %result = add <vscale x 4 x i32> %a, %extend
+  ret <vscale x 4 x i32> %result
+}
+
+define <vscale x 2 x i64> @zext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.2xi64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  %result = add <vscale x 2 x i64> %a, %extend
+  ret <vscale x 2 x i64> %result
+}
+
+define <vscale x 8 x i32> @zext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.8xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z2.s, p1/z, #1 // =0x1
+; CHECK-NEXT:    mov z3.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.s, z0.s, z3.s
+; CHECK-NEXT:    add z1.s, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  %result = add <vscale x 8 x i32> %a, %extend
+  ret <vscale x 8 x i32> %result
+}
+
+define <vscale x 16 x i32> @zext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: zext.add.16xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    punpkhi p2.h, p1.b
+; CHECK-NEXT:    punpklo p1.h, p1.b
+; CHECK-NEXT:    mov z4.s, p2/z, #1 // =0x1
+; CHECK-NEXT:    punpkhi p2.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z5.s, p1/z, #1 // =0x1
+; CHECK-NEXT:    mov z6.s, p2/z, #1 // =0x1
+; CHECK-NEXT:    mov z7.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    add z0.s, z0.s, z7.s
+; CHECK-NEXT:    add z1.s, z1.s, z6.s
+; CHECK-NEXT:    add z2.s, z2.s, z5.s
+; CHECK-NEXT:    add z3.s, z3.s, z4.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  %result = add <vscale x 16 x i32> %a, %extend
+  ret <vscale x 16 x i32> %result
+}
+
+define <vscale x 8 x i8> @zext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.8xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  %result = sub <vscale x 8 x i8> %a, %extend
+  ret <vscale x 8 x i8> %result
+}
+
+define <vscale x 4 x i16> @zext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.4xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  %result = sub <vscale x 4 x i16> %a, %extend
+  ret <vscale x 4 x i16> %result
+}
+
+define <vscale x 2 x i32> @zext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.2xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  %result = sub <vscale x 2 x i32> %a, %extend
+  ret <vscale x 2 x i32> %result
+}
+
+define <vscale x 16 x i8> @zext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.16xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.b, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  %result = sub <vscale x 16 x i8> %a, %extend
+  ret <vscale x 16 x i8> %result
+}
+
+define <vscale x 8 x i16> @zext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.8xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  %result = sub <vscale x 8 x i16> %a, %extend
+  ret <vscale x 8 x i16> %result
+}
+
+define <vscale x 4 x i32> @zext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.4xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  %result = sub <vscale x 4 x i32> %a, %extend
+  ret <vscale x 4 x i32> %result
+}
+
+define <vscale x 2 x i64> @zext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.2xi64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  %result = sub <vscale x 2 x i64> %a, %extend
+  ret <vscale x 2 x i64> %result
+}
+
+define <vscale x 8 x i32> @zext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.8xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpklo p1.h, p0.b
+; CHECK-NEXT:    punpkhi p0.h, p0.b
+; CHECK-NEXT:    mov z2.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z3.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z2.s
+; CHECK-NEXT:    add z1.s, z1.s, z3.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  %result = sub <vscale x 8 x i32> %a, %extend
+  ret <vscale x 8 x i32> %result
+}
+
+define <vscale x 16 x i32> @zext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: zext.sub.16xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpklo p1.h, p0.b
+; CHECK-NEXT:    punpkhi p0.h, p0.b
+; CHECK-NEXT:    punpklo p2.h, p1.b
+; CHECK-NEXT:    punpkhi p1.h, p1.b
+; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    punpklo p2.h, p0.b
+; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    punpkhi p0.h, p0.b
+; CHECK-NEXT:    add z0.s, z0.s, z4.s
+; CHECK-NEXT:    add z1.s, z1.s, z5.s
+; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z2.s, z2.s, z4.s
+; CHECK-NEXT:    add z3.s, z3.s, z5.s
+; CHECK-NEXT:    ret
+  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  %result = sub <vscale x 16 x i32> %a, %extend
+  ret <vscale x 16 x i32> %result
+}
+
+define <vscale x 8 x i8> @sext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.8xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  %result = add <vscale x 8 x i8> %a, %extend
+  ret <vscale x 8 x i8> %result
+}
+
+define <vscale x 4 x i16> @sext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.4xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  %result = add <vscale x 4 x i16> %a, %extend
+  ret <vscale x 4 x i16> %result
+}
+
+define <vscale x 2 x i32> @sext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.2xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  %result = add <vscale x 2 x i32> %a, %extend
+  ret <vscale x 2 x i32> %result
+}
+
+define <vscale x 16 x i8> @sext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.16xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.b, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  %result = add <vscale x 16 x i8> %a, %extend
+  ret <vscale x 16 x i8> %result
+}
+
+define <vscale x 8 x i16> @sext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.8xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  %result = add <vscale x 8 x i16> %a, %extend
+  ret <vscale x 8 x i16> %result
+}
+
+define <vscale x 4 x i32> @sext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.4xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  %result = add <vscale x 4 x i32> %a, %extend
+  ret <vscale x 4 x i32> %result
+}
+
+define <vscale x 2 x i64> @sext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.2xi64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  %result = add <vscale x 2 x i64> %a, %extend
+  ret <vscale x 2 x i64> %result
+}
+
+define <vscale x 8 x i32> @sext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.8xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z2.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z3.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z3.s
+; CHECK-NEXT:    add z1.s, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  %result = add <vscale x 8 x i32> %a, %extend
+  ret <vscale x 8 x i32> %result
+}
+
+define <vscale x 16 x i32> @sext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: sext.add.16xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    punpkhi p2.h, p1.b
+; CHECK-NEXT:    punpklo p1.h, p1.b
+; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    punpkhi p2.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z7.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z0.s, z0.s, z7.s
+; CHECK-NEXT:    add z1.s, z1.s, z6.s
+; CHECK-NEXT:    add z2.s, z2.s, z5.s
+; CHECK-NEXT:    add z3.s, z3.s, z4.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  %result = add <vscale x 16 x i32> %a, %extend
+  ret <vscale x 16 x i32> %result
+}
+
+define <vscale x 8 x i8> @sext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.8xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  %result = sub <vscale x 8 x i8> %a, %extend
+  ret <vscale x 8 x i8> %result
+}
+
+define <vscale x 4 x i16> @sext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.4xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  %result = sub <vscale x 4 x i16> %a, %extend
+  ret <vscale x 4 x i16> %result
+}
+
+define <vscale x 2 x i32> @sext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.2xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  %result = sub <vscale x 2 x i32> %a, %extend
+  ret <vscale x 2 x i32> %result
+}
+
+define <vscale x 16 x i8> @sext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.16xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.b, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  %result = sub <vscale x 16 x i8> %a, %extend
+  ret <vscale x 16 x i8> %result
+}
+
+define <vscale x 8 x i16> @sext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.8xi16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.h, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  %result = sub <vscale x 8 x i16> %a, %extend
+  ret <vscale x 8 x i16> %result
+}
+
+define <vscale x 4 x i32> @sext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.4xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.s, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  %result = sub <vscale x 4 x i32> %a, %extend
+  ret <vscale x 4 x i32> %result
+}
+
+define <vscale x 2 x i64> @sext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.2xi64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  %result = sub <vscale x 2 x i64> %a, %extend
+  ret <vscale x 2 x i64> %result
+}
+
+define <vscale x 8 x i32> @sext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.8xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z2.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z3.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.s, z0.s, z3.s
+; CHECK-NEXT:    sub z1.s, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  %result = sub <vscale x 8 x i32> %a, %extend
+  ret <vscale x 8 x i32> %result
+}
+
+define <vscale x 16 x i32> @sext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
+; CHECK-LABEL: sext.sub.16xi32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    punpkhi p1.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    punpkhi p2.h, p1.b
+; CHECK-NEXT:    punpklo p1.h, p1.b
+; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    punpkhi p2.h, p0.b
+; CHECK-NEXT:    punpklo p0.h, p0.b
+; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z7.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    sub z0.s, z0.s, z7.s
+; CHECK-NEXT:    sub z1.s, z1.s, z6.s
+; CHECK-NEXT:    sub z2.s, z2.s, z5.s
+; CHECK-NEXT:    sub z3.s, z3.s, z4.s
+; CHECK-NEXT:    ret
+  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  %result = sub <vscale x 16 x i32> %a, %extend
+  ret <vscale x 16 x i32> %result
+}
+
+attributes #0 = { "target-features"="+sve" }
-- 
2.7.4