From 1809414fe19a80afb1fb929e2e6a0c80b0f854f1 Mon Sep 17 00:00:00 2001 From: Pierre van Houtryve Date: Wed, 19 Oct 2022 09:01:19 +0000 Subject: [PATCH] [AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR Small bugfix. Currently harmless but a case in D134354 triggers it. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D136235 --- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 7f41e85..0a68966 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -686,13 +686,19 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const { // TODO: Can be improved? if (IsVector) { Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); - BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) - .addImm(0xFFFF) - .addReg(Src0); - BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) - .addReg(Src1) - .addImm(16) - .addReg(TmpReg); + auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) + .addImm(0xFFFF) + .addReg(Src0); + if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) + return false; + + MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) + .addReg(Src1) + .addImm(16) + .addReg(TmpReg); + if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) + return false; + MI.eraseFromParent(); return true; } -- 2.7.4