From 18092cf2c30efe6f4021b6ab29a581e172fa898d Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Wed, 7 Dec 2016 19:29:18 +0000 Subject: [PATCH] [X86] Do not assume "ri" instructions always have an immediate operand The second operand of an "ri" instruction may be an immediate, but it may also be a globalvariable, so we should make any assumptions. This fixes PR31271. Differential Revision: https://reviews.llvm.org/D27481 llvm-svn: 288964 --- llvm/lib/Target/X86/X86InstrBuilder.h | 5 +++++ llvm/lib/Target/X86/X86InstrInfo.cpp | 6 +++--- llvm/test/CodeGen/X86/pr31271.ll | 20 ++++++++++++++++++++ 3 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/X86/pr31271.ll diff --git a/llvm/lib/Target/X86/X86InstrBuilder.h b/llvm/lib/Target/X86/X86InstrBuilder.h index abf37d9..ba970bc 100644 --- a/llvm/lib/Target/X86/X86InstrBuilder.h +++ b/llvm/lib/Target/X86/X86InstrBuilder.h @@ -145,6 +145,11 @@ addOffset(const MachineInstrBuilder &MIB, int Offset) { return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); } +static inline const MachineInstrBuilder & +addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { + return MIB.addImm(1).addReg(0).addOperand(Offset).addReg(0); +} + /// addRegOffset - This function is used to add a memory reference of the form /// [Reg + Offset], i.e., one with no scale or index, but with a /// displacement. An example is: DWORD PTR [EAX + 4]. diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 07e9455e..303bd1e 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3878,7 +3878,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)) .addOperand(Dest) .addOperand(Src), - MI.getOperand(2).getImm()); + MI.getOperand(2)); break; case X86::ADD32ri: case X86::ADD32ri8: @@ -3901,7 +3901,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (ImplicitOp.getReg() != 0) MIB.addOperand(ImplicitOp); - NewMI = addOffset(MIB, MI.getOperand(2).getImm()); + NewMI = addOffset(MIB, MI.getOperand(2)); break; } case X86::ADD16ri: @@ -3915,7 +3915,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)) .addOperand(Dest) .addOperand(Src), - MI.getOperand(2).getImm()); + MI.getOperand(2)); break; } diff --git a/llvm/test/CodeGen/X86/pr31271.ll b/llvm/test/CodeGen/X86/pr31271.ll new file mode 100644 index 0000000..e38e176 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr31271.ll @@ -0,0 +1,20 @@ +; RUN: llc -mtriple=i386-unknown-linux-gnu < %s | FileCheck %s + +@c = external global [1 x i32], align 4 + +; CHECK-LABEL: fn1 +; CHECK: leal c(%eax), %ecx +define void @fn1(i32 %k) { + %g = getelementptr inbounds [1 x i32], [1 x i32]* @c, i32 0, i32 %k + %cmp = icmp ne i32* undef, %g + %z = zext i1 %cmp to i32 + store i32 %z, i32* undef, align 4 + %cmp2 = icmp eq i32* %g, null + br i1 %cmp2, label %u, label %r + +u: + unreachable + +r: + ret void +} -- 2.7.4