From 17bb8601e66d6ea6ab791ecbdfdf2a8efa6658a2 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 2 Jul 2014 15:40:58 +0200 Subject: [PATCH] clk: samsung: Add suspend/resume pm ops for audss clk controller Ensure the Exynos audio subsystem clock controller registers are preserved across suspend/resume. Change-Id: I57f4dcbbc9d02f7dfa2cd68508a9cefba010b9e5 Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4-audss.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4-audss.c b/drivers/clk/samsung/clk-exynos4-audss.c index 4522d00..28c18d0 100644 --- a/drivers/clk/samsung/clk-exynos4-audss.c +++ b/drivers/clk/samsung/clk-exynos4-audss.c @@ -51,22 +51,36 @@ static struct clk_onecell_data clk_data; static void __iomem *io_base; static struct clk *clks[AUDSS_CLK_MAX]; +#ifdef CONFIG_PM_SLEEP +static unsigned long reg_save[][2] = { + { AUDSS_CLKSRC, 0 }, + { AUDSS_CLKDIV, 0 }, + { AUDSS_CLKGATE, 0 }, +}; + static int samsung_audss_clk_suspend(void) { - /* TODO: */ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(reg_save); i++) + reg_save[i][1] = readl(io_base + reg_save[i][0]); + return 0; } static void samsung_audss_clk_resume(void) { - /* TODO: */ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(reg_save); i++) + writel(reg_save[i][1], io_base + reg_save[i][0]); } static struct syscore_ops samsung_audss_clk_syscore_ops = { .suspend = samsung_audss_clk_suspend, .resume = samsung_audss_clk_resume, }; - +#endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_OF static struct of_device_id audss_of_match[] __initdata = { -- 2.7.4