From 17a1df79bab5ef6f222aa5538b8e7c83f7ec1b7c Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 3 May 2021 17:39:28 -0700 Subject: [PATCH] anv, iris: Add Wa_16011773973 for DG2 Signed-off-by: Anuj Phogat Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_state.c | 9 ++ src/intel/vulkan/genX_pipeline.c | 175 ++++++++++++++++++---------------- 2 files changed, 101 insertions(+), 83 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index d01e345..ace28b3 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6105,6 +6105,15 @@ iris_upload_dirty_render_state(struct iris_context *ice, } if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) { + /* Wa_16011773973: + * If SOL is enabled and SO_DECL state has to be programmed, + * 1. Send 3D State SOL state with SOL disabled + * 2. Send SO_DECL NP state + * 3. Send 3D State SOL with SOL Enabled + */ + if (intel_device_info_is_dg2(&batch->screen->devinfo)) + iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol); + uint32_t *decl_list = ice->state.streamout + GENX(3DSTATE_STREAMOUT_length); iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2)); diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index b63d4cc..1ca9c49 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1523,89 +1523,6 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, else xfb_info = pipeline->shaders[MESA_SHADER_VERTEX]->xfb_info; -#if GFX_VER == 7 -# define streamout_state_dw pipeline->gfx7.streamout_state -#else -# define streamout_state_dw pipeline->gfx8.streamout_state -#endif - - struct GENX(3DSTATE_STREAMOUT) so = { - GENX(3DSTATE_STREAMOUT_header), - .RenderingDisable = - (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ? - 0 : rs_info->rasterizerDiscardEnable, - }; - - if (xfb_info) { - so.SOFunctionEnable = true; - so.SOStatisticsEnable = true; - - switch (vk_provoking_vertex_mode(rs_info)) { - case VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT: - so.ReorderMode = LEADING; - break; - - case VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT: - so.ReorderMode = TRAILING; - break; - - default: - unreachable("Invalid provoking vertex mode"); - } - - const VkPipelineRasterizationStateStreamCreateInfoEXT *stream_info = - vk_find_struct_const(rs_info, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT); - so.RenderStreamSelect = stream_info ? - stream_info->rasterizationStream : 0; - -#if GFX_VER >= 8 - so.Buffer0SurfacePitch = xfb_info->buffers[0].stride; - so.Buffer1SurfacePitch = xfb_info->buffers[1].stride; - so.Buffer2SurfacePitch = xfb_info->buffers[2].stride; - so.Buffer3SurfacePitch = xfb_info->buffers[3].stride; -#else - pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride; - pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride; - pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride; - pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride; - - /* On Gfx7, the SO buffer enables live in 3DSTATE_STREAMOUT which - * is a bit inconvenient because we don't know what buffers will - * actually be enabled until draw time. We do our best here by - * setting them based on buffers_written and we disable them - * as-needed at draw time by setting EndAddress = BaseAddress. - */ - so.SOBufferEnable0 = xfb_info->buffers_written & (1 << 0); - so.SOBufferEnable1 = xfb_info->buffers_written & (1 << 1); - so.SOBufferEnable2 = xfb_info->buffers_written & (1 << 2); - so.SOBufferEnable3 = xfb_info->buffers_written & (1 << 3); -#endif - - int urb_entry_read_offset = 0; - int urb_entry_read_length = - (prog_data->vue_map.num_slots + 1) / 2 - urb_entry_read_offset; - - /* We always read the whole vertex. This could be reduced at some - * point by reading less and offsetting the register index in the - * SO_DECLs. - */ - so.Stream0VertexReadOffset = urb_entry_read_offset; - so.Stream0VertexReadLength = urb_entry_read_length - 1; - so.Stream1VertexReadOffset = urb_entry_read_offset; - so.Stream1VertexReadLength = urb_entry_read_length - 1; - so.Stream2VertexReadOffset = urb_entry_read_offset; - so.Stream2VertexReadLength = urb_entry_read_length - 1; - so.Stream3VertexReadOffset = urb_entry_read_offset; - so.Stream3VertexReadLength = urb_entry_read_length - 1; - } - - if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) { - GENX(3DSTATE_STREAMOUT_pack)(NULL, streamout_state_dw, &so); - } else { - anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), _so) - _so = so; - } - if (xfb_info) { struct GENX(SO_DECL) so_decl[MAX_XFB_STREAMS][128]; int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0}; @@ -1687,6 +1604,15 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, sbs[xfb_info->buffer_to_stream[b]] |= 1 << b; } + /* Wa_16011773973: + * If SOL is enabled and SO_DECL state has to be programmed, + * 1. Send 3D State SOL state with SOL disabled + * 2. Send SO_DECL NP state + * 3. Send 3D State SOL with SOL Enabled + */ + if (intel_device_info_is_dg2(&pipeline->base.device->info)) + anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), so); + uint32_t *dw = anv_batch_emitn(&pipeline->base.batch, 3 + 2 * max_decls, GENX(3DSTATE_SO_DECL_LIST), .StreamtoBufferSelects0 = sbs[0], @@ -1708,6 +1634,89 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, }); } } + +#if GFX_VER == 7 +# define streamout_state_dw pipeline->gfx7.streamout_state +#else +# define streamout_state_dw pipeline->gfx8.streamout_state +#endif + + struct GENX(3DSTATE_STREAMOUT) so = { + GENX(3DSTATE_STREAMOUT_header), + .RenderingDisable = + (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ? + 0 : rs_info->rasterizerDiscardEnable, + }; + + if (xfb_info) { + so.SOFunctionEnable = true; + so.SOStatisticsEnable = true; + + switch (vk_provoking_vertex_mode(rs_info)) { + case VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT: + so.ReorderMode = LEADING; + break; + + case VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT: + so.ReorderMode = TRAILING; + break; + + default: + unreachable("Invalid provoking vertex mode"); + } + + const VkPipelineRasterizationStateStreamCreateInfoEXT *stream_info = + vk_find_struct_const(rs_info, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT); + so.RenderStreamSelect = stream_info ? + stream_info->rasterizationStream : 0; + +#if GFX_VER >= 8 + so.Buffer0SurfacePitch = xfb_info->buffers[0].stride; + so.Buffer1SurfacePitch = xfb_info->buffers[1].stride; + so.Buffer2SurfacePitch = xfb_info->buffers[2].stride; + so.Buffer3SurfacePitch = xfb_info->buffers[3].stride; +#else + pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride; + pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride; + pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride; + pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride; + + /* On Gfx7, the SO buffer enables live in 3DSTATE_STREAMOUT which + * is a bit inconvenient because we don't know what buffers will + * actually be enabled until draw time. We do our best here by + * setting them based on buffers_written and we disable them + * as-needed at draw time by setting EndAddress = BaseAddress. + */ + so.SOBufferEnable0 = xfb_info->buffers_written & (1 << 0); + so.SOBufferEnable1 = xfb_info->buffers_written & (1 << 1); + so.SOBufferEnable2 = xfb_info->buffers_written & (1 << 2); + so.SOBufferEnable3 = xfb_info->buffers_written & (1 << 3); +#endif + + int urb_entry_read_offset = 0; + int urb_entry_read_length = + (prog_data->vue_map.num_slots + 1) / 2 - urb_entry_read_offset; + + /* We always read the whole vertex. This could be reduced at some + * point by reading less and offsetting the register index in the + * SO_DECLs. + */ + so.Stream0VertexReadOffset = urb_entry_read_offset; + so.Stream0VertexReadLength = urb_entry_read_length - 1; + so.Stream1VertexReadOffset = urb_entry_read_offset; + so.Stream1VertexReadLength = urb_entry_read_length - 1; + so.Stream2VertexReadOffset = urb_entry_read_offset; + so.Stream2VertexReadLength = urb_entry_read_length - 1; + so.Stream3VertexReadOffset = urb_entry_read_offset; + so.Stream3VertexReadLength = urb_entry_read_length - 1; + } + + if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) { + GENX(3DSTATE_STREAMOUT_pack)(NULL, streamout_state_dw, &so); + } else { + anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_STREAMOUT), _so) + _so = so; + } } static uint32_t -- 2.7.4