From 172fb711a2336b62cf8d58bbb4b27dc71ca8c02d Mon Sep 17 00:00:00 2001 From: Andrew Burgess Date: Sat, 23 Feb 2019 22:07:47 +0200 Subject: [PATCH] gdb/riscv: Use legacy register numbers in default target description When the target description support was added to RISC-V, the register numbers assigned to the fflags, frm, and fcsr control registers in the default target descriptions didn't match the register numbers used by GDB before the target description support was added. What this means is that if a tools exists in the wild that is using hard-coded register number, setup to match GDB's old numbering, then this will have been broken (for fflags, frm, and fcsr) by the move to target descriptions. QEMU is such a tool. There are a couple of solutions that could be used to work around this issue: - The user can create their own xml description file with the register numbers setup to match their old tool, then load this by telling GDB 'set tdesc filename FILENAME'. - Update their old tool to use the newer default numbering scheme, or better yet add proper target description support to their tool. - We could have RISC-V GDB change to maintain the old defaults. This patch changes GDB back to using the old numbering scheme. This change is only visible to remote targets that don't supply their own xml description file and instead rely on GDB's default numbering. Note that even though 32bit-cpu.xml and 64bit-cpu.xml have changed, the corresponding .c file has not, this is because the numbering added to the registers in the xml files is number 0, this doesn't result in any new C code being generated . gdb/ChangeLog: * features/riscv/32bit-cpu.xml: Add register numbers. * features/riscv/32bit-fpu.c: Regenerate. * features/riscv/32bit-fpu.xml: Add register numbers. * features/riscv/64bit-cpu.xml: Add register numbers. * features/riscv/64bit-fpu.c: Regenerate. * features/riscv/64bit-fpu.xml: Add register numbers. --- gdb/ChangeLog | 9 +++++++++ gdb/features/riscv/32bit-cpu.xml | 6 +++++- gdb/features/riscv/32bit-fpu.c | 2 ++ gdb/features/riscv/32bit-fpu.xml | 12 ++++++++---- gdb/features/riscv/64bit-cpu.xml | 6 +++++- gdb/features/riscv/64bit-fpu.c | 2 ++ gdb/features/riscv/64bit-fpu.xml | 12 ++++++++---- 7 files changed, 39 insertions(+), 10 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index df94e75..1d747a7 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,12 @@ +2019-02-26 Andrew Burgess + + * features/riscv/32bit-cpu.xml: Add register numbers. + * features/riscv/32bit-fpu.c: Regenerate. + * features/riscv/32bit-fpu.xml: Add register numbers. + * features/riscv/64bit-cpu.xml: Add register numbers. + * features/riscv/64bit-fpu.c: Regenerate. + * features/riscv/64bit-fpu.xml: Add register numbers. + 2019-02-26 Kevin Buettner * NEWS: Mention two argument form of gdb.Value constructor. diff --git a/gdb/features/riscv/32bit-cpu.xml b/gdb/features/riscv/32bit-cpu.xml index 466f2c0..0d07aae 100644 --- a/gdb/features/riscv/32bit-cpu.xml +++ b/gdb/features/riscv/32bit-cpu.xml @@ -5,9 +5,13 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + - + diff --git a/gdb/features/riscv/32bit-fpu.c b/gdb/features/riscv/32bit-fpu.c index 22e80d6..a19780a 100644 --- a/gdb/features/riscv/32bit-fpu.c +++ b/gdb/features/riscv/32bit-fpu.c @@ -9,6 +9,7 @@ create_feature_riscv_32bit_fpu (struct target_desc *result, long regnum) struct tdesc_feature *feature; feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.fpu"); + regnum = 33; tdesc_create_reg (feature, "ft0", regnum++, 1, NULL, 32, "ieee_single"); tdesc_create_reg (feature, "ft1", regnum++, 1, NULL, 32, "ieee_single"); tdesc_create_reg (feature, "ft2", regnum++, 1, NULL, 32, "ieee_single"); @@ -41,6 +42,7 @@ create_feature_riscv_32bit_fpu (struct target_desc *result, long regnum) tdesc_create_reg (feature, "ft9", regnum++, 1, NULL, 32, "ieee_single"); tdesc_create_reg (feature, "ft10", regnum++, 1, NULL, 32, "ieee_single"); tdesc_create_reg (feature, "ft11", regnum++, 1, NULL, 32, "ieee_single"); + regnum = 66; tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 32, "int"); tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 32, "int"); tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 32, "int"); diff --git a/gdb/features/riscv/32bit-fpu.xml b/gdb/features/riscv/32bit-fpu.xml index 6a44b84..1eaae91 100644 --- a/gdb/features/riscv/32bit-fpu.xml +++ b/gdb/features/riscv/32bit-fpu.xml @@ -5,9 +5,13 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + - + @@ -40,7 +44,7 @@ - - - + + + diff --git a/gdb/features/riscv/64bit-cpu.xml b/gdb/features/riscv/64bit-cpu.xml index c4d83de..b8aa424 100644 --- a/gdb/features/riscv/64bit-cpu.xml +++ b/gdb/features/riscv/64bit-cpu.xml @@ -5,9 +5,13 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + - + diff --git a/gdb/features/riscv/64bit-fpu.c b/gdb/features/riscv/64bit-fpu.c index 8cbd748..b93cb4e 100644 --- a/gdb/features/riscv/64bit-fpu.c +++ b/gdb/features/riscv/64bit-fpu.c @@ -17,6 +17,7 @@ create_feature_riscv_64bit_fpu (struct target_desc *result, long regnum) field_type = tdesc_named_type (feature, "ieee_double"); tdesc_add_field (type_with_fields, "double", field_type); + regnum = 33; tdesc_create_reg (feature, "ft0", regnum++, 1, NULL, 64, "riscv_double"); tdesc_create_reg (feature, "ft1", regnum++, 1, NULL, 64, "riscv_double"); tdesc_create_reg (feature, "ft2", regnum++, 1, NULL, 64, "riscv_double"); @@ -49,6 +50,7 @@ create_feature_riscv_64bit_fpu (struct target_desc *result, long regnum) tdesc_create_reg (feature, "ft9", regnum++, 1, NULL, 64, "riscv_double"); tdesc_create_reg (feature, "ft10", regnum++, 1, NULL, 64, "riscv_double"); tdesc_create_reg (feature, "ft11", regnum++, 1, NULL, 64, "riscv_double"); + regnum = 66; tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 32, "int"); tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 32, "int"); tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 32, "int"); diff --git a/gdb/features/riscv/64bit-fpu.xml b/gdb/features/riscv/64bit-fpu.xml index fd14ebc..794854c 100644 --- a/gdb/features/riscv/64bit-fpu.xml +++ b/gdb/features/riscv/64bit-fpu.xml @@ -5,6 +5,10 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + @@ -13,7 +17,7 @@ - + @@ -46,7 +50,7 @@ - - - + + + -- 2.7.4