From 170a2398d2d80f0df0d6c664dddd237baf4408cf Mon Sep 17 00:00:00 2001 From: Su Sung Chung Date: Thu, 30 May 2019 14:59:03 -0400 Subject: [PATCH] drm/amd/display: make clk_mgr call enable_pme_wa [why] Before for raven and navi we are calling pp_smu functions for pme [how] refactor a code so we will call clk_mgr's enable_pme_wa function so we can use pme_wa for future asics. This way we don't need to worry about different ASIC since clk_mgr already have that information Signed-off-by: Su Sung Chung Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 14 +++++++++++ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 16 +++++++++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +++++----------------- 3 files changed, 35 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c index 31db9b55..183ca39 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c @@ -215,9 +215,23 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, } } +static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct pp_smu_funcs_rv *pp_smu = NULL; + + if (clk_mgr->pp_smu) { + pp_smu = &clk_mgr->pp_smu->rv_funcs; + + if (pp_smu->set_pme_wa_enable) + pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); + } +} + static struct clk_mgr_funcs rv1_clk_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .update_clocks = rv1_update_clocks, + .enable_pme_wa = rv1_enable_pme_wa, }; static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index df59cb7..08a774f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -303,10 +303,24 @@ void dcn2_init_clocks(struct clk_mgr *clk_mgr) memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); } +void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct pp_smu_funcs_nv *pp_smu = NULL; + + if (clk_mgr->pp_smu) { + pp_smu = &clk_mgr->pp_smu->nv_funcs; + + if (pp_smu->set_pme_wa_enable) + pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); + } +} + static struct clk_mgr_funcs dcn2_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .update_clocks = dcn2_update_clocks, - .init_clocks = dcn2_init_clocks + .init_clocks = dcn2_init_clocks, + .enable_pme_wa = dcn2_enable_pme_wa }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index edda426..940e74b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -958,30 +958,12 @@ void hwss_edp_backlight_control( edp_receiver_ready_T9(link); } -// Static helper function which calls the correct function -// based on pp_smu version -static void set_pme_wa_enable_by_version(struct dc *dc) -{ - struct pp_smu_funcs *pp_smu = NULL; - - if (dc->res_pool->pp_smu) - pp_smu = dc->res_pool->pp_smu; - - if (pp_smu) { - if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable) - pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->rv_funcs.pp_smu)); -#ifdef CONFIG_DRM_AMD_DC_DCN2_0 - else if (pp_smu->ctx.ver == PP_SMU_VER_NV && pp_smu->nv_funcs.set_pme_wa_enable) - pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->nv_funcs.pp_smu)); -#endif - } -} - void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) { /* notify audio driver for audio modes of monitor */ struct dc *core_dc = pipe_ctx->stream->ctx->dc; struct pp_smu_funcs *pp_smu = NULL; + struct clk_mgr *clk_mgr = core_dc->clk_mgr; unsigned int i, num_audio = 1; if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) @@ -999,9 +981,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); - if (num_audio >= 1 && pp_smu != NULL) + if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ - set_pme_wa_enable_by_version(core_dc); + clk_mgr->funcs->enable_pme_wa(clk_mgr); /* un-mute audio */ /* TODO: audio should be per stream rather than per link */ pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( @@ -1015,6 +997,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) { struct dc *dc = pipe_ctx->stream->ctx->dc; struct pp_smu_funcs *pp_smu = NULL; + struct clk_mgr *clk_mgr = dc->clk_mgr; if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) return; @@ -1043,9 +1026,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); pipe_ctx->stream_res.audio = NULL; } - if (pp_smu != NULL) + if (clk_mgr->funcs->enable_pme_wa) /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ - set_pme_wa_enable_by_version(dc); + clk_mgr->funcs->enable_pme_wa(clk_mgr); /* TODO: notify audio driver for if audio modes list changed * add audio mode list change flag */ -- 2.7.4