From 16d02dc907c5717b5f47076bb90ae3795e73b59f Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 9 Apr 2013 11:07:06 +0000 Subject: [PATCH] gas/ 2013-04-09 Jan Beulich * gas/config/tc-arm.c (do_vmrs): Accept all control registers. Use local variable Rt in more places. (do_vmsr): Accept all control registers. gas/testsuite/ 2013-04-09 Jan Beulich * gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2, and C15. * gas/arm/vfp1xD.d: Update accordingly. --- gas/ChangeLog | 6 ++++++ gas/config/tc-arm.c | 34 ++++++++-------------------------- gas/testsuite/ChangeLog | 6 ++++++ gas/testsuite/gas/arm/vfp1xD.d | 20 +++++++++++++------- gas/testsuite/gas/arm/vfp1xD.s | 8 +++++++- 5 files changed, 40 insertions(+), 34 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 48ac7e5..5918b60 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2013-04-09 Jan Beulich + * gas/config/tc-arm.c (do_vmrs): Accept all control registers. + Use local variable Rt in more places. + (do_vmsr): Accept all control registers. + +2013-04-09 Jan Beulich + * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix if there was none specified for moves between scalar and core register. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 9b8d8c1..78fa733 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -8256,32 +8256,22 @@ do_vmrs (void) { unsigned Rt = inst.operands[0].reg; - if (thumb_mode && inst.operands[0].reg == REG_SP) + if (thumb_mode && Rt == REG_SP) { inst.error = BAD_SP; return; } /* APSR_ sets isvec. All other refs to PC are illegal. */ - if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) + if (!inst.operands[0].isvec && Rt == REG_PC) { inst.error = BAD_PC; return; } - switch (inst.operands[1].reg) - { - case 0: /* FPSID */ - case 1: /* FPSCR */ - case 6: /* MVFR1 */ - case 7: /* MVFR0 */ - case 8: /* FPEXC */ - inst.instruction |= (inst.operands[1].reg << 16); - break; - default: - first_error (_("operand 1 must be a VFP extension System Register")); - } - + /* If we get through parsing the register name, we just insert the number + generated into the instruction without further validation. */ + inst.instruction |= (inst.operands[1].reg << 16); inst.instruction |= (Rt << 12); } @@ -8298,17 +8288,9 @@ do_vmsr (void) return; } - switch (inst.operands[0].reg) - { - case 0: /* FPSID */ - case 1: /* FPSCR */ - case 8: /* FPEXC */ - inst.instruction |= (inst.operands[0].reg << 16); - break; - default: - first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC")); - } - + /* If we get through parsing the register name, we just insert the number + generated into the instruction without further validation. */ + inst.instruction |= (inst.operands[0].reg << 16); inst.instruction |= (Rt << 12); } diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 510927f..ba42c25 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2013-04-09 Jan Beulich + * gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2, + and C15. + * gas/arm/vfp1xD.d: Update accordingly. + +2013-04-09 Jan Beulich + * gas/arm/neon-omit.s: Add tests for suffix less VMOV. * gas/arm/neon-omit.d: Update accordingly. diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d index 62b1957..8eaf9ae 100644 --- a/gas/testsuite/gas/arm/vfp1xD.d +++ b/gas/testsuite/gas/arm/vfp1xD.d @@ -280,10 +280,16 @@ Disassembly of section .text: 0+438 <[^>]*> eee1ea10 vmsr fpscr, lr 0+43c <[^>]*> eee01a10 vmsr fpsid, r1 0+440 <[^>]*> eee82a10 vmsr fpexc, r2 -0+444 <[^>]*> eef03a10 vmrs r3, fpsid -0+448 <[^>]*> eef64a10 vmrs r4, mvfr1 -0+44c <[^>]*> eef75a10 vmrs r5, mvfr0 -0+450 <[^>]*> eef86a10 vmrs r6, fpexc -0+454 <[^>]*> e1a00000 nop ; \(mov r0, r0\) -0+458 <[^>]*> e1a00000 nop ; \(mov r0, r0\) -0+45c <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def +0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def +0+44c <[^>]*> eeef5a10 vmsr (c15|), r5 +0+450 <[^>]*> eef03a10 vmrs r3, fpsid +0+454 <[^>]*> eef64a10 vmrs r4, mvfr1 +0+458 <[^>]*> eef75a10 vmrs r5, mvfr0 +0+45c <[^>]*> eef86a10 vmrs r6, fpexc +0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def +0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def +0+468 <[^>]*> eeff9a10 vmrs r9, (c15|) +0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s index 0bf58b2..0e603e9 100644 --- a/gas/testsuite/gas/arm/vfp1xD.s +++ b/gas/testsuite/gas/arm/vfp1xD.s @@ -381,13 +381,19 @@ F: vmsr FPSCR, r12 vmsr FPSCR, r14 - @ Priviledged externsions to VMSR/VMRS instructions + @ Priviledged extensions to VMSR/VMRS instructions vmsr FPSID, r1 vmsr FPEXC, r2 + vmsr FPINST, r3 + vmsr FPINST2, r4 + vmsr C15, r5 vmrs r3, FPSID vmrs r4, MVFR1 vmrs r5, MVFR0 vmrs r6, FPEXC + vmrs r7, FPINST + vmrs r8, FPINST2 + vmrs r9, C15 nop nop -- 2.7.4