From 16ad7e4eef7180a5ccddc111d06bba276849526e Mon Sep 17 00:00:00 2001 From: Dong-Heon Jung Date: Sun, 11 Jun 2023 03:27:37 +0900 Subject: [PATCH] [RISC-V] Fix errors in vm (#87310) * [RISC-V] Fix JUMP block size * [RISC-V] Update constant values * [RISC-V] Fix decodeJump * [RISC-V] Update constant values more self-describing --- src/coreclr/vm/callingconvention.h | 4 +++- src/coreclr/vm/riscv64/asmconstants.h | 3 ++- src/coreclr/vm/riscv64/cgencpu.h | 8 ++++---- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/coreclr/vm/callingconvention.h b/src/coreclr/vm/callingconvention.h index 6841f3e..f647945 100644 --- a/src/coreclr/vm/callingconvention.h +++ b/src/coreclr/vm/callingconvention.h @@ -926,7 +926,9 @@ public: { // TODO-RISCV64: support SIMD. // Dividing by 8 as size of each register in FloatArgumentRegisters is 8 bytes. - pLoc->m_idxFloatReg = (argOffset - TransitionBlock::GetOffsetOfFloatArgumentRegisters()) / 8; + const int floatRegOfsInBytes = (argOffset - TransitionBlock::GetOffsetOfFloatArgumentRegisters()); + _ASSERTE((floatRegOfsInBytes % FLOAT_REGISTER_SIZE) == 0); + pLoc->m_idxFloatReg = floatRegOfsInBytes / FLOAT_REGISTER_SIZE; assert(!m_argTypeHandle.IsHFA()); diff --git a/src/coreclr/vm/riscv64/asmconstants.h b/src/coreclr/vm/riscv64/asmconstants.h index 12aedda2..1089bfe 100644 --- a/src/coreclr/vm/riscv64/asmconstants.h +++ b/src/coreclr/vm/riscv64/asmconstants.h @@ -188,9 +188,10 @@ ASMCONSTANTS_C_ASSERT(CONTEXT_Pc == offsetof(T_CONTEXT,Pc)) ASMCONSTANTS_C_ASSERT(SIZEOF__FaultingExceptionFrame == sizeof(FaultingExceptionFrame)); ASMCONSTANTS_C_ASSERT(FaultingExceptionFrame__m_fFilterExecuted == offsetof(FaultingExceptionFrame, m_fFilterExecuted)); -#define SIZEOF__FixupPrecode 40 +#define SIZEOF__FixupPrecode 32 #define MethodDesc_ALIGNMENT_SHIFT 3 +ASMCONSTANTS_C_ASSERT(SIZEOF__FixupPrecode == sizeof(FixupPrecode)); ASMCONSTANTS_C_ASSERT(MethodDesc_ALIGNMENT_SHIFT == MethodDesc::ALIGNMENT_SHIFT); #define ResolveCacheElem__pMT 0x00 diff --git a/src/coreclr/vm/riscv64/cgencpu.h b/src/coreclr/vm/riscv64/cgencpu.h index d665103..0280015 100644 --- a/src/coreclr/vm/riscv64/cgencpu.h +++ b/src/coreclr/vm/riscv64/cgencpu.h @@ -31,8 +31,8 @@ extern PCODE GetPreStubEntryPoint(); #define STACK_ALIGN_SIZE 16 -#define JUMP_ALLOCATE_SIZE 16 // # bytes to allocate for a jump instruction -#define BACK_TO_BACK_JUMP_ALLOCATE_SIZE 16 // # bytes to allocate for a back to back jump instruction +#define JUMP_ALLOCATE_SIZE 40 // # bytes to allocate for a jump instruction +#define BACK_TO_BACK_JUMP_ALLOCATE_SIZE 40 // # bytes to allocate for a back to back jump instruction #define HAS_NDIRECT_IMPORT_PRECODE 1 @@ -54,7 +54,7 @@ extern PCODE GetPreStubEntryPoint(); #define CALLDESCR_ARGREGS 1 // CallDescrWorker has ArgumentRegister parameter #define CALLDESCR_FPARGREGS 1 // CallDescrWorker has FloatArgumentRegisters parameter -#define FLOAT_REGISTER_SIZE 16 // each register in FloatArgumentRegisters is 16 bytes. +#define FLOAT_REGISTER_SIZE 8 // each register in FloatArgumentRegisters is 8 bytes. // Given a return address retrieved during stackwalk, // this is the offset by which it should be decremented to arrive at the callsite. @@ -263,7 +263,7 @@ inline PCODE decodeJump(PCODE pCode) TADDR pInstr = PCODEToPINSTR(pCode); - return *dac_cast(pInstr + 2*sizeof(DWORD)); + return *dac_cast(pInstr + 4 * sizeof(UINT32)); } //------------------------------------------------------------------------ -- 2.7.4