From 16a05f19039ea3ac6257c2ad7697e7ecff36f4cc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Sat, 6 May 2023 17:03:22 +0200 Subject: [PATCH] aco: Don't allow any VALU instruction to write m0. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Fixes: d5398b62da1913e7224c826da0dbd5fa88436f18 Signed-off-by: Timur Kristóf Reviewed-by: Georg Lehmann Part-of: --- src/amd/compiler/aco_ir.cpp | 9 +++++---- src/amd/compiler/aco_ir.h | 2 +- src/amd/compiler/aco_register_allocation.cpp | 2 +- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp index 03f6931..6c9e64f 100644 --- a/src/amd/compiler/aco_ir.cpp +++ b/src/amd/compiler/aco_ir.cpp @@ -480,22 +480,23 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx) } bool -can_write_m0(amd_gfx_level gfx_level, const aco_ptr& instr) +can_write_m0(const aco_ptr& instr) { if (instr->isSALU()) return true; + /* VALU can't write m0 on any GPU generations. */ if (instr->isVALU()) - return gfx_level >= GFX9; + return false; switch (instr->opcode) { case aco_opcode::p_parallelcopy: case aco_opcode::p_extract: case aco_opcode::p_insert: + /* These pseudo instructions are implemented with SALU when writing m0. */ return true; - case aco_opcode::p_reload: - return gfx_level >= GFX9; default: + /* Assume that no other instructions can write m0. */ return false; } } diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index a39e949..528e0c3 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1804,7 +1804,7 @@ bool instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op); uint8_t get_gfx11_true16_mask(aco_opcode op); bool can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr& instr, bool pre_ra); bool can_use_DPP(const aco_ptr& instr, bool pre_ra, bool dpp8); -bool can_write_m0(amd_gfx_level gfx_level, const aco_ptr& instr); +bool can_write_m0(const aco_ptr& instr); /* updates "instr" and returns the old instruction (or NULL if no update was needed) */ aco_ptr convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr& instr); aco_ptr convert_to_DPP(aco_ptr& instr, bool dpp8); diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index fba6e1c..0b36010 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -1656,7 +1656,7 @@ get_reg(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, } if (ctx.assignments[temp.id()].m0) { if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, m0) && - can_write_m0(ctx.program->gfx_level, instr)) + can_write_m0(instr)) return m0; } -- 2.7.4