From 1613c5fddd424a5d18b97d21bb2ede608133e205 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:19 +0300 Subject: [PATCH] drm/msm/dpu: drop UBWC configuration As the DPU driver has switched to fetching data from MDSS driver, we can now drop the UBWC and highest_bank_bit parts of the DPU hw catalog. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550058/ Link: https://lore.kernel.org/r/20230728213320.97309-7-dmitry.baryshkov@linaro.org --- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------ .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 ------ .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 ----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 ------ .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 25 ---------------------- 17 files changed, 128 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 92530ae..43c47a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -21,11 +21,6 @@ static const struct dpu_caps msm8998_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg msm8998_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, @@ -323,7 +318,6 @@ static const struct dpu_mdss_version msm8998_mdss_ver = { const struct dpu_mdss_cfg dpu_msm8998_cfg = { .mdss_ver = &msm8998_mdss_ver, .caps = &msm8998_dpu_caps, - .ubwc = &msm8998_ubwc_cfg, .mdp = &msm8998_mdp, .ctl_count = ARRAY_SIZE(msm8998_ctl), .ctl = msm8998_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 3034c1b..88a5177 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -21,11 +21,6 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg sdm845_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -340,7 +335,6 @@ static const struct dpu_mdss_version sdm845_mdss_ver = { const struct dpu_mdss_cfg dpu_sdm845_cfg = { .mdss_ver = &sdm845_mdss_ver, .caps = &sdm845_dpu_caps, - .ubwc = &sdm845_ubwc_cfg, .mdp = &sdm845_mdp, .ctl_count = ARRAY_SIZE(sdm845_ctl), .ctl = sdm845_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 3745c15..99acaf9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -21,11 +21,6 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg sm8150_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -383,7 +378,6 @@ static const struct dpu_mdss_version sm8150_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8150_cfg = { .mdss_ver = &sm8150_mdss_ver, .caps = &sm8150_dpu_caps, - .ubwc = &sm8150_ubwc_cfg, .mdp = &sm8150_mdp, .ctl_count = ARRAY_SIZE(sm8150_ctl), .ctl = sm8150_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 6291568..f3de210 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -21,11 +21,6 @@ static const struct dpu_caps sc8180x_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x3, -}; - static const struct dpu_mdp_cfg sc8180x_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -410,7 +405,6 @@ static const struct dpu_mdss_version sc8180x_mdss_ver = { const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .mdss_ver = &sc8180x_mdss_ver, .caps = &sc8180x_dpu_caps, - .ubwc = &sc8180x_ubwc_cfg, .mdp = &sc8180x_mdp, .ctl_count = ARRAY_SIZE(sc8180x_ctl), .ctl = sc8180x_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index e922668..2491eed1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm6125_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x1, -}; - static const struct dpu_mdp_cfg sm6125_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -208,7 +202,6 @@ static const struct dpu_mdss_version sm6125_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6125_cfg = { .mdss_ver = &sm6125_mdss_ver, .caps = &sm6125_dpu_caps, - .ubwc = &sm6125_ubwc_cfg, .mdp = &sm6125_mdp, .ctl_count = ARRAY_SIZE(sm6125_ctl), .ctl = sm6125_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 9751b39..5f9b437 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sm8250_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -398,7 +392,6 @@ static const struct dpu_mdss_version sm8250_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8250_cfg = { .mdss_ver = &sm8250_mdss_ver, .caps = &sm8250_dpu_caps, - .ubwc = &sm8250_ubwc_cfg, .mdp = &sm8250_mdp, .ctl_count = ARRAY_SIZE(sm8250_ctl), .ctl = sm8250_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index a9464b8..d030c08 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -17,11 +17,6 @@ static const struct dpu_caps sc7180_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .highest_bank_bit = 0x3, -}; - static const struct dpu_mdp_cfg sc7180_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -212,7 +207,6 @@ static const struct dpu_mdss_version sc7180_mdss_ver = { const struct dpu_mdss_cfg dpu_sc7180_cfg = { .mdss_ver = &sc7180_mdss_ver, .caps = &sc7180_dpu_caps, - .ubwc = &sc7180_ubwc_cfg, .mdp = &sc7180_mdp, .ctl_count = ARRAY_SIZE(sc7180_ctl), .ctl = sc7180_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index ae7cd96..7e60001 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -17,12 +17,6 @@ static const struct dpu_caps sm6115_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x7, -}; - static const struct dpu_mdp_cfg sm6115_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -144,7 +138,6 @@ static const struct dpu_mdss_version sm6115_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6115_cfg = { .mdss_ver = &sm6115_mdss_ver, .caps = &sm6115_dpu_caps, - .ubwc = &sm6115_ubwc_cfg, .mdp = &sm6115_mdp, .ctl_count = ARRAY_SIZE(sm6115_ctl), .ctl = sm6115_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index a13305c..cf5db6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm6350_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .ubwc_swizzle = 6, - .highest_bank_bit = 1, -}; - static const struct dpu_mdp_cfg sm6350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -215,7 +209,6 @@ static const struct dpu_mdss_version sm6350_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6350_cfg = { .mdss_ver = &sm6350_mdss_ver, .caps = &sm6350_dpu_caps, - .ubwc = &sm6350_ubwc_cfg, .mdp = &sm6350_mdp, .ctl_count = ARRAY_SIZE(sm6350_ctl), .ctl = sm6350_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index bb297c3..87a03aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -16,10 +16,6 @@ static const struct dpu_caps qcm2290_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg qcm2290_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -134,7 +130,6 @@ static const struct dpu_mdss_version qcm2290_mdss_ver = { const struct dpu_mdss_cfg dpu_qcm2290_cfg = { .mdss_ver = &qcm2290_mdss_ver, .caps = &qcm2290_dpu_caps, - .ubwc = &qcm2290_ubwc_cfg, .mdp = &qcm2290_mdp, .ctl_count = ARRAY_SIZE(qcm2290_ctl), .ctl = qcm2290_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 014a56e..a327e21 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -18,12 +18,6 @@ static const struct dpu_caps sm6375_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .ubwc_swizzle = 6, - .highest_bank_bit = 1, -}; - static const struct dpu_mdp_cfg sm6375_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -154,7 +148,6 @@ static const struct dpu_mdss_version sm6375_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6375_cfg = { .mdss_ver = &sm6375_mdss_ver, .caps = &sm6375_dpu_caps, - .ubwc = &sm6375_ubwc_cfg, .mdp = &sm6375_mdp, .ctl_count = ARRAY_SIZE(sm6375_ctl), .ctl = sm6375_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 941b585..c906b68 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -19,11 +19,6 @@ static const struct dpu_caps sm8350_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ -}; - static const struct dpu_mdp_cfg sm8350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -391,7 +386,6 @@ static const struct dpu_mdss_version sm8350_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8350_cfg = { .mdss_ver = &sm8350_mdss_ver, .caps = &sm8350_dpu_caps, - .ubwc = &sm8350_ubwc_cfg, .mdp = &sm8350_mdp, .ctl_count = ARRAY_SIZE(sm8350_ctl), .ctl = sm8350_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index b18bb7c..2bf9f34 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -17,12 +17,6 @@ static const struct dpu_caps sc7280_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sc7280_mdp = { .name = "top_0", .base = 0x0, .len = 0x2014, @@ -260,7 +254,6 @@ static const struct dpu_mdss_version sc7280_mdss_ver = { const struct dpu_mdss_cfg dpu_sc7280_cfg = { .mdss_ver = &sc7280_mdss_ver, .caps = &sc7280_dpu_caps, - .ubwc = &sc7280_ubwc_cfg, .mdp = &sc7280_mdp, .ctl_count = ARRAY_SIZE(sc7280_ctl), .ctl = sc7280_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index b08096f..ccd0477 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -19,12 +19,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 2, - .ubwc_swizzle = 6, -}; - static const struct dpu_mdp_cfg sc8280xp_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -453,7 +447,6 @@ static const struct dpu_mdss_version sc8280xp_mdss_ver = { const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { .mdss_ver = &sc8280xp_mdss_ver, .caps = &sc8280xp_dpu_caps, - .ubwc = &sc8280xp_ubwc_cfg, .mdp = &sc8280xp_mdp, .ctl_count = ARRAY_SIZE(sc8280xp_ctl), .ctl = sc8280xp_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 9e0ad71..2b2e9d48 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm8450_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sm8450_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -414,7 +408,6 @@ static const struct dpu_mdss_version sm8450_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8450_cfg = { .mdss_ver = &sm8450_mdss_ver, .caps = &sm8450_dpu_caps, - .ubwc = &sm8450_ubwc_cfg, .mdp = &sm8450_mdp, .ctl_count = ARRAY_SIZE(sm8450_ctl), .ctl = sm8450_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 2a19e4c..833be11 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -19,11 +19,6 @@ static const struct dpu_caps sm8550_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ -}; - static const struct dpu_mdp_cfg sm8550_mdp = { .name = "top_0", .base = 0, .len = 0x494, @@ -428,7 +423,6 @@ static const struct dpu_mdss_version sm8550_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8550_cfg = { .mdss_ver = &sm8550_mdss_ver, .caps = &sm8550_dpu_caps, - .ubwc = &sm8550_ubwc_cfg, .mdp = &sm8550_mdp, .ctl_count = ARRAY_SIZE(sm8550_ctl), .ctl = sm8550_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index c72ed0e..0989aaa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -29,16 +29,6 @@ #define MAX_XIN_COUNT 16 /** - * Supported UBWC feature versions - */ -enum { - DPU_HW_UBWC_VER_10 = 0x100, - DPU_HW_UBWC_VER_20 = 0x200, - DPU_HW_UBWC_VER_30 = 0x300, - DPU_HW_UBWC_VER_40 = 0x400, -}; - -/** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats @@ -503,19 +493,6 @@ struct dpu_mdp_cfg { struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; -/** - * struct dpu_ubwc_cfg - UBWC and memory configuration - * - * @ubwc_version UBWC feature version (0x0 for not supported) - * @highest_bank_bit: UBWC parameter - * @ubwc_swizzle: ubwc default swizzle setting - */ -struct dpu_ubwc_cfg { - u32 ubwc_version; - u32 highest_bank_bit; - u32 ubwc_swizzle; -}; - /* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss @@ -817,8 +794,6 @@ struct dpu_mdss_cfg { const struct dpu_caps *caps; - const struct dpu_ubwc_cfg *ubwc; - const struct dpu_mdp_cfg *mdp; u32 ctl_count; -- 2.7.4