From 1610730faf589649b94d35dd88ac754b99d8afc4 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 29 Jan 2015 17:26:56 +0000 Subject: [PATCH] [Hexagon] Deleting old variants of intrinsics and adding missing tests. llvm-svn: 227474 --- llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 131 +++++++++------------ llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td | 100 ---------------- llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td | 15 +-- llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll | 21 ++++ llvm/test/CodeGen/Hexagon/intrinsics/cr.ll | 76 ++++++++++-- llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll | 8 ++ 6 files changed, 155 insertions(+), 196 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 6359c9f..e4d8c44 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -597,6 +597,38 @@ def : T_R_pat; def : T_R_pat; /******************************************************************** +* ALU32/PRED * +*********************************************************************/ +// Compare +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; + +def : T_RI_pat; +def : T_RI_pat; +def : T_RI_pat; + +def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)), + (i32 (C2_cmpgti (I32:$src1), + (DEC_CONST_SIGNED s8ExtPred:$src2)))>; + +def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)), + (i32 (C2_cmpgtui (I32:$src1), + (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>; + +// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0. +def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)), + (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>; + +def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1), + (I32:$src2))), + (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>; + +def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1), + (I32:$src2))), + (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>; + +/******************************************************************** * ALU64/ALU * *********************************************************************/ def: T_RR_pat; @@ -608,6 +640,10 @@ def: T_PP_pat; def: T_PP_pat; def: T_PP_pat; +def: T_PP_pat; +def: T_PP_pat; +def: T_PP_pat; + def: T_PP_pat; def: T_RR_pat; @@ -622,6 +658,27 @@ def : T_PRR_pat ; def : T_PRR_pat ; def : T_PRR_pat ; +/******************************************************************** +* CR * +*********************************************************************/ +class qi_CRInst_qi_pat : + Pat<(i32 (IntID IntRegs:$Rs)), + (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>; + +class qi_CRInst_qiqi_pat : + Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)), + (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>; + +def: qi_CRInst_qi_pat; +def: qi_CRInst_qi_pat; +def: qi_CRInst_qi_pat; + +def: qi_CRInst_qiqi_pat; +def: qi_CRInst_qiqi_pat; +def: qi_CRInst_qiqi_pat; +def: qi_CRInst_qiqi_pat; +def: qi_CRInst_qiqi_pat; + // Multiply 32x32 and use lower result def : T_RRI_pat ; def : T_RRI_pat ; @@ -1331,40 +1388,6 @@ class di_LDInstPI_diu4 "$src1 = $dst">; /******************************************************************** -* ALU32/PERM * -*********************************************************************/ - -// ALU32 / PERM / Mux. -def HEXAGON_C2_mux: - si_ALU32_qisisi <"mux", int_hexagon_C2_mux>; - -/******************************************************************** -* ALU32/PRED * -*********************************************************************/ - -// ALU32 / PRED / Compare. -def HEXAGON_C2_cmpeq: - qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>; -def HEXAGON_C2_cmpeqi: - qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>; -def HEXAGON_C2_cmpgei: - qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>; -def HEXAGON_C2_cmpgeui: - qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>; -def HEXAGON_C2_cmpgt: - qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>; -def HEXAGON_C2_cmpgti: - qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>; -def HEXAGON_C2_cmpgtu: - qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>; -def HEXAGON_C2_cmpgtui: - qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>; -def HEXAGON_C2_cmplt: - qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>; -def HEXAGON_C2_cmpltu: - qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>; - -/******************************************************************** * ALU32/VH * *********************************************************************/ @@ -1393,18 +1416,6 @@ def HEXAGON_A2_svsubhs: def HEXAGON_A2_svsubuhs: si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>; -/******************************************************************** -* ALU64/ALU * -*********************************************************************/ - -// ALU64 / ALU / Compare. -def HEXAGON_C2_cmpeqp: - qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>; -def HEXAGON_C2_cmpgtp: - qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>; -def HEXAGON_C2_cmpgtup: - qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>; - // ALU64 / ALU / Transfer register. def HEXAGON_A2_tfrp: di_ALU64_di <"", int_hexagon_A2_tfrp>; @@ -1564,34 +1575,6 @@ def HEXAGON_A2_vsubw: def HEXAGON_A2_vsubws: di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>; - -/******************************************************************** -* CR * -*********************************************************************/ - -// CR / Logical reductions on predicates. -def HEXAGON_C2_all8: - qi_SInst_qi <"all8", int_hexagon_C2_all8>; -def HEXAGON_C2_any8: - qi_SInst_qi <"any8", int_hexagon_C2_any8>; - -// CR / Logical operations on predicates. -def HEXAGON_C2_pxfer_map: - qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>; -def HEXAGON_C2_and: - qi_SInst_qiqi <"and", int_hexagon_C2_and>; -def HEXAGON_C2_andn: - qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>; -def HEXAGON_C2_not: - qi_SInst_qi <"not", int_hexagon_C2_not>; -def HEXAGON_C2_or: - qi_SInst_qiqi <"or", int_hexagon_C2_or>; -def HEXAGON_C2_orn: - qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>; -def HEXAGON_C2_xor: - qi_SInst_qiqi <"xor", int_hexagon_C2_xor>; - - /******************************************************************** * MTYPE/ALU * *********************************************************************/ diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td index 17571d3..58a702c 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td @@ -206,103 +206,3 @@ def : T_RI_pat ; def : T_RR_pat ; def : T_P_pat ; - -class qi_neg_ALU32_sisi - : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; - -class qi_neg_ALU32_sis10 - : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; - -class qi_neg_ALU32_siu9 - : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; - -// -// SInst Classes. -// -class qi_neg_SInst_qiqi - : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; - -class qi_SInst_qi_andqiqi_neg - : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, and($src2, !$src3)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3))]>; - -class qi_SInst_qi_andqiqi - : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, and($src2, $src3)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3))]>; - -class qi_SInst_qi_orqiqi_neg - : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, or($src2, !$src3)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3))]>; - -class qi_SInst_qi_orqiqi - : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, or($src2, $src3)")), - [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - IntRegs:$src3))]>; - -/******************************************************************** -* ALU32/PRED * -*********************************************************************/ - -// ALU32 / PRED / Conditional Shift Halfword. -// ALU32 / PRED / Conditional Sign Extend. -// ALU32 / PRED / Conditional Zero Extend. -// ALU32 / PRED / Compare. -def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>; -def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>; -def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>; - -def: T_RI_pat; -def: T_RI_pat; -def: T_RI_pat; - - -/******************************************************************** -* CR * -*********************************************************************/ - -// CR / Corner Detection Acceleration. -def Hexagon_C4_fastcorner9: - qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>; -def Hexagon_C4_fastcorner9_not: - qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>; - -// CR / Logical Operations On Predicates. -def Hexagon_C4_and_andn: - qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>; -def Hexagon_C4_and_and: - qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>; -def Hexagon_C4_and_orn: - qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>; -def Hexagon_C4_and_or: - qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>; -def Hexagon_C4_or_andn: - qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>; -def Hexagon_C4_or_and: - qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>; -def Hexagon_C4_or_orn: - qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>; -def Hexagon_C4_or_or: - qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td index b2abe96..390e910 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -17,6 +17,9 @@ def : T_FF_pat; def : T_FF_pat; def : T_F_pat ; +def: qi_CRInst_qiqi_pat; +def: qi_CRInst_qiqi_pat; + def : T_P_pat ; def : T_PI_pat ; @@ -104,10 +107,6 @@ class di_MInst_diu4_rnd !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")), [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>; -def HEXAGON_C4_fastcorner9: - qi_SInst_qiqi <"fastcorner9", int_hexagon_C4_fastcorner9>; -def HEXAGON_C4_fastcorner9_not: - qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>; def HEXAGON_M5_vrmpybuu: di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>; def HEXAGON_M5_vrmacbuu: @@ -132,11 +131,3 @@ def HEXAGON_A5_vaddhubs: si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>; def HEXAGON_S5_vasrhrnd_goodsyntax: di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>; -def HEXAGON_F2_sfcmpeq: - qi_SInst_sfsf <"sfcmp.eq", int_hexagon_F2_sfcmpeq>; -def HEXAGON_F2_sfcmpgt: - qi_SInst_sfsf <"sfcmp.gt", int_hexagon_F2_sfcmpgt>; -def HEXAGON_F2_sfcmpge: - qi_SInst_sfsf <"sfcmp.ge", int_hexagon_F2_sfcmpge>; -def HEXAGON_F2_sfcmpuo: - qi_SInst_sfsf <"sfcmp.uo", int_hexagon_F2_sfcmpuo>; diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll index 2edb5fd..a9cc01c 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll @@ -2,6 +2,20 @@ ; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM ; Combine words into doubleword +declare i64 @llvm.hexagon.A4.combineri(i32, i32) +define i64 @A4_combineri(i32 %a) { + %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0) + ret i64 %z +} +; CHECK: = combine(r0, #0) + +declare i64 @llvm.hexagon.A4.combineir(i32, i32) +define i64 @A4_combineir(i32 %a) { + %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a) + ret i64 %z +} +; CHECK: = combine(#0, r0) + declare i64 @llvm.hexagon.A2.combineii(i32, i32) define i64 @A2_combineii() { %z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0) @@ -59,6 +73,13 @@ define i32 @C2_muxir(i32 %a, i32 %b) { } ; CHECK: r0 = mux(p0, r1, #0) +declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) +define i32 @C2_mux(i32 %a, i32 %b, i32 %c) { + %z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: r0 = mux(p0, r1, r2) + ; Shift word by 16 declare i32 @llvm.hexagon.A2.aslh(i32) define i32 @A2_aslh(i32 %a) { diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll b/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll index f0d6da5..9bdcb25 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll @@ -7,14 +7,14 @@ define i32 @C4_fastcorner9(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = fastcorner9(r0, r1) +; CHECK: p0 = fastcorner9(p0, p1) declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32) define i32 @C4_fastcorner9_not(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = !fastcorner9(r0, r1) +; CHECK: p0 = !fastcorner9(p0, p1) ; Logical reductions on predicates declare i32 @llvm.hexagon.C2.any8(i32) @@ -22,7 +22,7 @@ define i32 @C2_any8(i32 %a) { %z = call i32@llvm.hexagon.C2.any8(i32 %a) ret i32 %z } -; CHECK: p0 = any8(r0) +; CHECK: p0 = any8(p0) declare i32 @llvm.hexagon.C2.all8(i32) define i32 @C2_all8(i32 %a) { @@ -30,7 +30,7 @@ define i32 @C2_all8(i32 %a) { ret i32 %z } -; CHECK: p0 = all8(r0) +; CHECK: p0 = all8(p0) ; Logical operations on predicates declare i32 @llvm.hexagon.C2.and(i32, i32) @@ -38,39 +38,95 @@ define i32 @C2_and(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = and(r0, r1) +; CHECK: p0 = and(p0, p1) + +declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) +define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = and(p0, and(p1, p2)) declare i32 @llvm.hexagon.C2.or(i32, i32) define i32 @C2_or(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = or(r0, r1) +; CHECK: p0 = or(p0, p1) + +declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32) +define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = and(p0, or(p1, p2)) declare i32 @llvm.hexagon.C2.xor(i32, i32) define i32 @C2_xor(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = xor(r0, r1) +; CHECK: p0 = xor(p0, p1) + +declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32) +define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = or(p0, and(p1, p2)) declare i32 @llvm.hexagon.C2.andn(i32, i32) define i32 @C2_andn(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = and(r0, !r1) +; CHECK: p0 = and(p0, !p1) + +declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32) +define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = or(p0, or(p1, p2)) + +declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32) +define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = and(p0, and(p1, !p2)) + +declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32) +define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = and(p0, or(p1, !p2)) declare i32 @llvm.hexagon.C2.not(i32) define i32 @C2_not(i32 %a) { %z = call i32@llvm.hexagon.C2.not(i32 %a) ret i32 %z } -; CHECK: p0 = not(r0) +; CHECK: p0 = not(p0) + +declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32) +define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = or(p0, and(p1, !p2)) declare i32 @llvm.hexagon.C2.orn(i32, i32) define i32 @C2_orn(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b) ret i32 %z } -; CHECK: p0 = or(r0, !r1) +; CHECK: p0 = or(p0, !p1) + +declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32) +define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) { + %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c) + ret i32 %z +} +; CHECK: p0 = or(p0, or(p1, !p2)) diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll index 5485440..febf4a6 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll @@ -543,3 +543,11 @@ define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) { ret i32 %z } ; CHECK: r0 = sub(r0.h, r1.h):sat:<<16 + +; Sign extend word to doubleword +declare i64 @llvm.hexagon.A2.sxtw(i32) +define i64 @A2_sxtw(i32 %a) { + %z = call i64 @llvm.hexagon.A2.sxtw(i32 %a) + ret i64 %z +} +; CHECK: = sxtw(r0) -- 2.7.4