From 1601dd97edc643e4f033851729a9f5ba01655e2b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 1 Dec 2016 12:07:43 +0100 Subject: [PATCH] davinci: omapl138_lcdk: increase PLL0 frequency The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows. Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses. Signed-off-by: Bartosz Golaszewski Reviewed-by: Tom Rini --- include/configs/omapl138_lcdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 9e11f7d..7c2f414 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -75,7 +75,7 @@ #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 -#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL0_PLLM 37 #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* -- 2.7.4