From 15fd4ca41d44b92966425b628eba12e475a484dc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 13 Sep 2021 10:00:21 +0200 Subject: [PATCH] dt-bindings: mfd: brcm,cru: Add clkset syscon MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit CRU has a shared register that is used e.g. to control USB 2.0 PHY block access. It's a single 32 b register. Document it as syscon so it can be used with a regmap. Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/brcm,cru.yaml | 8 ++++++++ Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/brcm,cru.yaml b/Documentation/devicetree/bindings/mfd/brcm,cru.yaml index fc1317a..bf4e585 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,cru.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,cru.yaml @@ -39,6 +39,9 @@ patternProperties: '^clock-controller@[a-f0-9]+$': $ref: ../clock/brcm,iproc-clocks.yaml + '^syscon@[a-f0-9]+$': + $ref: syscon.yaml + '^thermal@[a-f0-9]+$': $ref: ../thermal/brcm,ns-thermal.yaml @@ -73,6 +76,11 @@ examples: "iprocfast", "sata1", "sata2"; }; + syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pinctrl { compatible = "brcm,bcm4708-pinmux"; offset = <0x1c0>; diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index abe3fd8..0dcffc2 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - brcm,cru-clkset - hisilicon,dsa-subctrl - hisilicon,hi6220-sramctrl - hisilicon,pcie-sas-subctrl -- 2.7.4