From 151a030063898e5c8b03b40c3a96b073db0b0dc7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 13 Apr 2022 17:47:22 +0800 Subject: [PATCH] arm: set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid Since COUNTER_FREQUENCY is obselete, so set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid Signed-off-by: Peng Fan Reviewed-by: Philipp Tomsich --- arch/arm/cpu/armv7/ls102xa/psci.S | 2 +- arch/arm/cpu/armv7/ls102xa/timer.c | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- arch/arm/cpu/armv7/sunxi/psci.c | 2 +- arch/arm/cpu/armv8/start.S | 4 ++-- arch/arm/mach-rockchip/rk3036-board-spl.c | 2 +- arch/arm/mach-rockchip/spl.c | 2 +- arch/arm/mach-rockchip/tpl.c | 2 +- board/sunxi/board.c | 6 +++--- 9 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index 531cfb0..3956178 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -36,7 +36,7 @@ .align 5 -#define ONE_MS (COUNTER_FREQUENCY / 1000) +#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000) #define RESET_WAIT (30 * ONE_MS) .globl psci_version diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index d79bf10..c6126b1 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -65,7 +65,7 @@ int timer_init(void) /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); - freq = COUNTER_FREQUENCY; + freq = CONFIG_COUNTER_FREQUENCY; asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); /* Set PL1 Physical Timer Ctrl */ diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 1773fae..39aeeb4 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -189,11 +189,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef COUNTER_FREQUENCY +#if CONFIG_COUNTER_FREQUENCY mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =COUNTER_FREQUENCY + ldreq r1, =CONFIG_COUNTER_FREQUENCY mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 1ac50f5..d1bd6b9 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -57,7 +57,7 @@ static u32 __secure cp15_read_cntp_ctl(void) return val; } -#define ONE_MS (COUNTER_FREQUENCY / 1000) +#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000) static void __secure __mdelay(u32 ms) { diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 6a6a4f8..d328e8c 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -138,9 +138,9 @@ pie_fixup_done: 0: msr daifclr, #0x4 /* Unmask SError interrupts */ -#ifdef COUNTER_FREQUENCY +#if CONFIG_COUNTER_FREQUENCY branch_if_not_highest_el x0, 4f - ldr x0, =COUNTER_FREQUENCY + ldr x0, =CONFIG_COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ #endif diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 6eb89e1..73f6d24 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -20,7 +20,7 @@ void rockchip_stimer_init(void) { asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); + : : "r"(CONFIG_COUNTER_FREQUENCY)); writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index eda2248..30be640 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -88,7 +88,7 @@ __weak void rockchip_stimer_init(void) return; #ifndef CONFIG_ARM64 asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); + : : "r"(CONFIG_COUNTER_FREQUENCY)); #endif writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 8126587..ed46a9a 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -39,7 +39,7 @@ __weak void rockchip_stimer_init(void) #ifndef CONFIG_ARM64 asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); + : : "r"(CONFIG_COUNTER_FREQUENCY)); #endif writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 8932415..371ed9e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -202,14 +202,14 @@ int board_init(void) * we avoid the risk of writing to it. */ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); - if (freq != COUNTER_FREQUENCY) { + if (freq != CONFIG_COUNTER_FREQUENCY) { debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", - freq, COUNTER_FREQUENCY); + freq, CONFIG_COUNTER_FREQUENCY); #ifdef CONFIG_NON_SECURE printf("arch timer frequency is wrong, but cannot adjust it\n"); #else asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); + : : "r"(CONFIG_COUNTER_FREQUENCY)); #endif } } -- 2.7.4