From 1515308a542b17d9ddf5403a836fbe8d17b9893d Mon Sep 17 00:00:00 2001
From: Sjoerd Meijer <smeijer@nvidia.com>
Date: Mon, 5 Dec 2022 15:36:24 +0000
Subject: [PATCH] [LoopFlatten] Precommit test for GH issue #59339. NFC.

---
 llvm/test/Transforms/LoopFlatten/pr59339.ll | 59 +++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopFlatten/pr59339.ll

diff --git a/llvm/test/Transforms/LoopFlatten/pr59339.ll b/llvm/test/Transforms/LoopFlatten/pr59339.ll
new file mode 100644
index 0000000..52ce4ba
--- /dev/null
+++ b/llvm/test/Transforms/LoopFlatten/pr59339.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -S -opaque-pointers -loop-flatten -verify-loop-info -verify-dom-info -verify-scev -verify | FileCheck %s
+
+; FIXME: This incorrectly triggers, thus resulting in a miscompilation.
+; The problem is that there is a linear use of the induction variable, i*3+j,
+; but only the part i*3 is used for indexing.
+
+define void @test0(i16* %0, i16* %1) {
+; CHECK-LABEL: @test0(
+; CHECK-NEXT:    [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 3, 2
+; CHECK-NEXT:    br label [[DOTPREHEADER:%.*]]
+; CHECK:       .preheader:
+; CHECK-NEXT:    [[TMP3:%.*]] = phi i64 [ 0, [[TMP2:%.*]] ], [ [[TMP7:%.*]], [[TMP6:%.*]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = mul i64 [[TMP3]], 3
+; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr i16, ptr [[TMP1:%.*]], i64 [[TMP4]]
+; CHECK-NEXT:    br label [[TMP9:%.*]]
+; CHECK:       6:
+; CHECK-NEXT:    [[TMP7]] = add i64 [[TMP3]], 1
+; CHECK-NEXT:    [[TMP8:%.*]] = icmp slt i64 [[TMP7]], [[FLATTEN_TRIPCOUNT]]
+; CHECK-NEXT:    br i1 [[TMP8]], label [[DOTPREHEADER]], label [[TMP16:%.*]]
+; CHECK:       9:
+; CHECK-NEXT:    [[TMP10:%.*]] = phi i64 [ 0, [[DOTPREHEADER]] ]
+; CHECK-NEXT:    [[TMP11:%.*]] = load i16, ptr [[TMP5]], align 2
+; CHECK-NEXT:    [[TMP12:%.*]] = add i64 [[TMP10]], [[TMP4]]
+; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i16, ptr [[TMP0:%.*]], i64 [[TMP3]]
+; CHECK-NEXT:    store i16 [[TMP11]], ptr [[TMP13]], align 2
+; CHECK-NEXT:    [[TMP14:%.*]] = add nuw nsw i64 [[TMP10]], 1
+; CHECK-NEXT:    [[TMP15:%.*]] = icmp ult i64 [[TMP14]], 3
+; CHECK-NEXT:    br label [[TMP6]]
+; CHECK:       16:
+; CHECK-NEXT:    ret void
+;
+2:
+  br label %.preheader
+
+.preheader:
+  %3 = phi i64 [ 0, %2 ], [ %7, %6 ]
+  %4 = mul i64 %3, 3
+  %5 = getelementptr i16, ptr %1, i64 %4
+  br label %9
+
+6:
+  %7 = add i64 %3, 1
+  %8 = icmp slt i64 %7, 2
+  br i1 %8, label %.preheader, label %16
+
+9:
+  %10 = phi i64 [ 0, %.preheader ], [ %14, %9 ]
+  %11 = load i16, ptr %5, align 2
+  %12 = add i64 %10, %4
+  %13 = getelementptr i16, ptr %0, i64 %12
+  store i16 %11, ptr %13, align 2
+  %14 = add nuw nsw i64 %10, 1
+  %15 = icmp ult i64 %14, 3
+  br i1 %15, label %9, label %6
+
+16:
+  ret void
+}
-- 
2.7.4