From 14f1ac69f5dd6d3faa3ac6cb9be0fa38f763e1dd Mon Sep 17 00:00:00 2001 From: uweigand Date: Wed, 14 Dec 2005 16:08:57 +0000 Subject: [PATCH] 2005-12-14 Adrian Straetling * config/s390/s390.md ("extenddi2", "extendsi2"): Merge. ("*extendqidi2_extimm", "*extendqisi2_extimm"): Merge. ("*extendqidi2", "*extendqisi2") Merge. ("*extendqidi2_short_displ", "*extendqisi2_short_displ"): Merge. ("zero_extendhidi2", "zero_extendqidi2"): Merge. ("*zero_extenddi2_extimm", "*zero_extendsi2_extimm"): Merge. Move some patterns to retain partial ordering. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@108515 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 +++ gcc/config/s390/s390.md | 203 +++++++++++++++++------------------------------- 2 files changed, 82 insertions(+), 131 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2a56930..68b7795 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,15 @@ 2005-12-14 Adrian Straetling + * config/s390/s390.md ("extenddi2", "extendsi2"): Merge. + ("*extendqidi2_extimm", "*extendqisi2_extimm"): Merge. + ("*extendqidi2", "*extendqisi2") Merge. + ("*extendqidi2_short_displ", "*extendqisi2_short_displ"): Merge. + ("zero_extendhidi2", "zero_extendqidi2"): Merge. + ("*zero_extenddi2_extimm", "*zero_extendsi2_extimm"): Merge. + Move some patterns to retain partial ordering. + +2005-12-14 Adrian Straetling + * config/s390/s390.md ("atype", "length"): Rewrite. ("*insv_reg_imm", "*insv_reg_extimm"): Add mode. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index dab9b58..3c634b3 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -2650,32 +2650,37 @@ [(set_attr "op_type" "RRE,RXY")]) ; -; extend(hi|qi)di2 instruction pattern(s). +; extend(hi|qi)(si|di)2 instruction pattern(s). ; -(define_expand "extenddi2" - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] +(define_expand "extend2" + [(set (match_operand:DSI 0 "register_operand" "") + (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] "" { - if (!TARGET_64BIT) + if (mode == DImode && !TARGET_64BIT) { rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_extendsi2 (tmp, operands[1])); + emit_insn (gen_extendsi2 (tmp, operands[1])); emit_insn (gen_extendsidi2 (operands[0], tmp)); DONE; } else if (!TARGET_EXTIMM) { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - - GET_MODE_BITSIZE (mode)); - operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); - emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount)); + rtx bitcount = GEN_INT (GET_MODE_BITSIZE (mode) - + GET_MODE_BITSIZE (mode)); + + operands[1] = gen_lowpart (mode, operands[1]); + emit_insn (gen_ashl3 (operands[0], operands[1], bitcount)); + emit_insn (gen_ashr3 (operands[0], operands[0], bitcount)); DONE; } }) +; +; extendhidi2 instruction pattern(s). +; + (define_insn "*extendhidi2_extimm" [(set (match_operand:DI 0 "register_operand" "=d,d") (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] @@ -2692,60 +2697,10 @@ "lgh\t%0,%1" [(set_attr "op_type" "RXY")]) -(define_insn "*extendqidi2_extimm" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] - "TARGET_64BIT && TARGET_EXTIMM" - "@ - lgbr\t%0,%1 - lgb\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) - -(define_insn "*extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" - "lgb\t%0,%1" - [(set_attr "op_type" "RXY")]) - -(define_insn_and_split "*extendqidi2_short_displ" - [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" - "#" - "&& reload_completed" - [(parallel - [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM)) - (clobber (reg:CC CC_REGNUM))]) - (parallel - [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) - (clobber (reg:CC CC_REGNUM))])] -{ - operands[1] = adjust_address (operands[1], BLKmode, 0); - set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); -}) - ; -; extend(hi|qi)si2 instruction pattern(s). +; extendhisi2 instruction pattern(s). ; -(define_expand "extendsi2" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] - "" -{ - if (!TARGET_EXTIMM) - { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - - GET_MODE_BITSIZE(mode)); - operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount)); - emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount)); - DONE; - } -}) - (define_insn "*extendhisi2_extimm" [(set (match_operand:SI 0 "register_operand" "=d,d,d") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))] @@ -2765,38 +2720,44 @@ lhy\t%0,%1" [(set_attr "op_type" "RX,RXY")]) -(define_insn "*extendqisi2_extimm" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] +; +; extendqi(si|di)2 instruction pattern(s). +; + +(define_insn "*extendqi2_extimm" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))] "TARGET_EXTIMM" "@ - lbr\t%0,%1 - lb\t%0,%1" + lbr\t%0,%1 + lb\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) -(define_insn "*extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM" - "lb\t%0,%1" +(define_insn "*extendqi2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))] + "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" + "lb\t%0,%1" [(set_attr "op_type" "RXY")]) -(define_insn_and_split "*extendqisi2_short_displ" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) +(define_insn_and_split "*extendqi2_short_displ" + [(set (match_operand:GPR 0 "register_operand" "=d") + (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) (clobber (reg:CC CC_REGNUM))] - "!TARGET_LONG_DISPLACEMENT" + "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM)) + [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) + [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) (clobber (reg:CC CC_REGNUM))])] { operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); + operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) + - GET_MODE_BITSIZE (QImode)); }) ; @@ -2832,49 +2793,6 @@ [(set_attr "op_type" "RRE,RXY")]) ; -; zero_extend(hi|qi)di2 instruction pattern(s). -; - -(define_expand "zero_extenddi2" - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] - "" -{ - if (!TARGET_64BIT) - { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendsi2 (tmp, operands[1])); - emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); - DONE; - } - else if (!TARGET_EXTIMM) - { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - - GET_MODE_BITSIZE(mode)); - operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); - emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); - DONE; - } -}) - -(define_insn "*zero_extenddi2_extimm" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] - "TARGET_64BIT && TARGET_EXTIMM" - "@ - llgr\t%0,%1 - llg\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) - -(define_insn "*zero_extenddi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))] - "TARGET_64BIT && !TARGET_EXTIMM" - "llg\t%0,%1" - [(set_attr "op_type" "RXY")]) - -; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). ; @@ -2931,9 +2849,32 @@ "") ; -; zero_extend(hi|qi)si2 instruction pattern(s). +; zero_extend(hi|qi)(si|di)2 instruction pattern(s). ; +(define_expand "zero_extenddi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] + "" +{ + if (!TARGET_64BIT) + { + rtx tmp = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendsi2 (tmp, operands[1])); + emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); + DONE; + } + else if (!TARGET_EXTIMM) + { + rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - + GET_MODE_BITSIZE(mode)); + operands[1] = gen_lowpart (DImode, operands[1]); + emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); + emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); + DONE; + } +}) + (define_expand "zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] @@ -2945,21 +2886,21 @@ emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1))); DONE; -} + } }) -(define_insn "*zero_extendsi2_extimm" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] +(define_insn "*zero_extend2_extimm" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] "TARGET_EXTIMM" "@ - llr\t%0,%1 - ll\t%0,%1" + llr\t%0,%1 + ll\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) -(define_insn "*zero_extendsi2_64" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))] +(define_insn "*zero_extend2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg\t%0,%1" [(set_attr "op_type" "RXY")]) -- 2.7.4