From 14c6dfdfe2da38653797c7070d882e7546f1c067 Mon Sep 17 00:00:00 2001
From: Sam Parker <sam.parker@arm.com>
Date: Fri, 2 Aug 2019 07:32:28 +0000
Subject: [PATCH] [NFC][ARM][ParallelDSP] Remove ValueList

We only care about the first element in the list.

llvm-svn: 367660
---
 llvm/lib/Target/ARM/ARMParallelDSP.cpp | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
index 5e7627f..1a1e2db 100644
--- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
@@ -49,7 +49,6 @@ namespace {
 
   using MulCandList     = SmallVector<std::unique_ptr<MulCandidate>, 8>;
   using ReductionList   = SmallVector<Reduction, 8>;
-  using ValueList       = SmallVector<Value*, 8>;
   using MemInstList     = SmallVector<LoadInst*, 8>;
   using PMACPair        = std::pair<MulCandidate*,MulCandidate*>;
   using PMACPairList    = SmallVector<PMACPair, 8>;
@@ -64,8 +63,8 @@ namespace {
     bool          Exchange = false;
     bool          ReadOnly = true;
 
-    MulCandidate(Instruction *I, ValueList &lhs, ValueList &rhs) :
-      Root(I), LHS(lhs.front()), RHS(rhs.front()) { }
+    MulCandidate(Instruction *I, Value *lhs, Value *rhs) :
+      Root(I), LHS(lhs), RHS(rhs) { }
 
     bool HasTwoLoadInputs() const {
       return isa<LoadInst>(LHS) && isa<LoadInst>(RHS);
@@ -95,7 +94,7 @@ namespace {
 
     /// Record a MulCandidate, rooted at a Mul instruction, that is a part of
     /// this reduction.
-    void InsertMul(Instruction *I, ValueList &LHS, ValueList &RHS) {
+    void InsertMul(Instruction *I, Value *LHS, Value *RHS) {
       Muls.push_back(make_unique<MulCandidate>(I, LHS, RHS));
     }
 
@@ -171,7 +170,7 @@ namespace {
     std::map<LoadInst*, std::unique_ptr<WidenedLoad>> WideLoads;
 
     template<unsigned>
-    bool IsNarrowSequence(Value *V, ValueList &VL);
+    bool IsNarrowSequence(Value *V, Value *&Src);
 
     bool RecordMemoryOps(BasicBlock *BB);
     void InsertParallelMACs(Reduction &Reduction);
@@ -283,7 +282,7 @@ bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
 // TODO: we currently only collect i16, and will support i8 later, so that's
 // why we check that types are equal to MaxBitWidth, and not <= MaxBitWidth.
 template<unsigned MaxBitWidth>
-bool ARMParallelDSP::IsNarrowSequence(Value *V, ValueList &VL) {
+bool ARMParallelDSP::IsNarrowSequence(Value *V, Value *&Src) {
   if (auto *SExt = dyn_cast<SExtInst>(V)) {
     if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
       return false;
@@ -293,8 +292,7 @@ bool ARMParallelDSP::IsNarrowSequence(Value *V, ValueList &VL) {
       if (!LoadPairs.count(Ld) && !OffsetLoads.count(Ld))
         return false;
 
-      VL.push_back(Ld);
-      VL.push_back(SExt);
+      Src = Ld;
       return true;
     }
   }
@@ -461,8 +459,8 @@ bool ARMParallelDSP::MatchSMLAD(Function &F) {
       Value *MulOp0 = I->getOperand(0);
       Value *MulOp1 = I->getOperand(1);
       if (isa<SExtInst>(MulOp0) && isa<SExtInst>(MulOp1)) {
-        ValueList LHS;
-        ValueList RHS;
+        Value *LHS = nullptr;
+        Value *RHS = nullptr;
         if (IsNarrowSequence<16>(MulOp0, LHS) &&
             IsNarrowSequence<16>(MulOp1, RHS)) {
           R.InsertMul(I, LHS, RHS);
-- 
2.7.4