From 13c033bc630a2df51931d16ea5fb81710ad2e0b2 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 7 Dec 2018 10:03:39 +0000 Subject: [PATCH] ARM: dts: imx7ulp: add HSRUN mode clocks i.MX7ULP can switch CPU between RUN mode and HSRUN mode by programming SMC1 register, different clock sources will be used for CPU in different modes, so SMC1 can be abstracted as a clock controller for CPU clock switch, this patch adds support for it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 931b275..b86daf7 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -199,9 +199,13 @@ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; - smc1: smc1@40410000 { + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; }; pcc3: clock-controller@40b30000 { -- 2.7.4