From 13907f4bd2eba88229c83bef3daee13734df83b0 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Fri, 10 Feb 2023 14:26:07 +0800 Subject: [PATCH] RISC-V: Add vssrl.vv C API tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vssrl_vv-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv-3.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vssrl_vv-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c | 160 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c | 160 +++++++++++++++++++++ 18 files changed, 2880 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c new file mode 100644 index 0000000..8e38ad6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c new file mode 100644 index 0000000..39a28ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2(op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1(op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2(op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4(op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2(op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1(op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2(op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4(op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2(op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1(op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2(op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4(op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8(op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1(op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2(op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4(op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c new file mode 100644 index 0000000..0a8ea53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2(op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1(op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2(op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4(op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2(op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1(op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2(op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4(op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2(op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1(op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2(op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4(op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8(op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1(op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2(op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4(op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c new file mode 100644 index 0000000..998a709 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_m(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_m(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_m(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_m(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_m(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_m(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_m(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_m(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_m(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_m(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_m(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_m(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_m(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_m(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_m(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_m(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_m(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_m(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_m(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_m(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_m(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c new file mode 100644 index 0000000..6715b0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_m(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_m(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_m(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_m(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_m(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_m(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_m(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_m(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_m(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_m(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_m(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_m(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_m(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_m(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_m(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_m(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_m(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_m(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_m(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_m(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_m(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c new file mode 100644 index 0000000..23184a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_m(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_m(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_m(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_m(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_m(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_m(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_m(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_m(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_m(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_m(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_m(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_m(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_m(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_m(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_m(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_m(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_m(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_m(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_m(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_m(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_m(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c new file mode 100644 index 0000000..4e24cc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c new file mode 100644 index 0000000..e76b6f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c new file mode 100644 index 0000000..12981e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c new file mode 100644 index 0000000..4051360 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c new file mode 100644 index 0000000..f13c3c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c new file mode 100644 index 0000000..4177750 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c new file mode 100644 index 0000000..d4973e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c new file mode 100644 index 0000000..c7633c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c new file mode 100644 index 0000000..aec1417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c new file mode 100644 index 0000000..ee2b194 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c new file mode 100644 index 0000000..9491525 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c new file mode 100644 index 0000000..6046f35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf8_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m1_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m4_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u8m8_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m1_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m4_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u16m8_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m1_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m4_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u32m8_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m1_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m2_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m4_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vssrl_vv_u64m8_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.7.4