From 138463d3c3e3134aa43863ac8a5a18e60b9cb43a Mon Sep 17 00:00:00 2001 From: Joshua Ashton Date: Fri, 10 Sep 2021 22:05:06 +0100 Subject: [PATCH] radv: Fix DCC image store check Doesn't seem to be causing any issues right now but could with modifiers potentially. Matches what is in RadeonSI where the comment is also shamelessly stolen from. Signed-off-by: Joshua Ashton Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_image.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 7a1b9b3..664882a 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -295,16 +295,18 @@ radv_image_use_dcc_image_stores(const struct radv_device *device, const struct r if (device->physical_device->rad_info.chip_class < GFX10) return false; - if ((device->physical_device->rad_info.family == CHIP_NAVI12 || - device->physical_device->rad_info.family == CHIP_NAVI14) && - !image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks) { - /* Do not enable DCC image stores because INDEPENDENT_128B_BLOCKS is required, and 64B is used - * for displayable DCC on NAVI12-14. - */ - return false; - } - - return true; + /* DCC image stores require the following settings: + * - INDEPENDENT_64B_BLOCKS = 0 + * - INDEPENDENT_128B_BLOCKS = 1 + * - MAX_COMPRESSED_BLOCK_SIZE = 128B + * - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used) + * + * The same limitations apply to SDMA compressed stores because + * SDMA uses the same DCC codec. + */ + return !image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks && + image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks && + image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B; } /* -- 2.7.4