From 12f82acc9e55a16334d303ae2b88609bdcbf13e5 Mon Sep 17 00:00:00 2001 From: Bill Seurer Date: Wed, 6 Feb 2019 16:29:56 +0000 Subject: [PATCH] vsx-vector-6.p7.c: Update instruction counts and target. 2019-02-06 Bill Seurer * gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction counts and target. * gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction counts and target. * gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction counts and target. From-SVN: r268585 --- gcc/testsuite/ChangeLog | 9 ++++++++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c | 24 ++++++++-------------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c | 23 ++++++++------------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c | 4 ++-- 4 files changed, 28 insertions(+), 32 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5763b9b..e14e7ae 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2019-02-06 Bill Seurer + + * gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction + counts and target. + * gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction + counts and target. + * gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction + counts and target. + 2019-02-06 Richard Biener PR tree-optimization/89182 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c index ab6e557..68f40db 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c @@ -1,28 +1,20 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { lp64 && be } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ - /* Expected instruction counts for Power 7 */ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 6 } } */ /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c index 82fd45e..bd9eda7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c @@ -1,16 +1,15 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power8" } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - /* Expected instruction counts for Power 8. */ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 { target be } } } */ /* We generate xxlor instructions for many reasons other than or'ing vector operands or calling __builtin_vec_or(), which means we cannot rely on @@ -18,16 +17,12 @@ xxlor instruction was generated. */ /* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 6 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 4 } } */ /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c index 0fcd153..8146fdc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power9" } */ @@ -8,7 +8,7 @@ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 } } */ /* We generate xxlor instructions for many reasons other than or'ing vector operands or calling __builtin_vec_or(), which means we cannot rely on -- 2.7.4