From 12a1910e875865492b2515d4bdcde48b1a2e72fd Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 12 Jun 2015 20:47:06 +0000 Subject: [PATCH] R600/SI: Add assembler support for FLAT instructions - Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637 --- llvm/docs/R600Usage.rst | 5 + llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp | 65 +++ llvm/lib/Target/R600/CIInstructions.td | 125 +++--- llvm/lib/Target/R600/SIInstrFormats.td | 1 + llvm/lib/Target/R600/SIInstrInfo.td | 92 ++-- llvm/test/CodeGen/R600/flat-address-space.ll | 2 +- llvm/test/MC/R600/flat.s | 477 +++++++++++++++++++++ 7 files changed, 677 insertions(+), 90 deletions(-) create mode 100644 llvm/test/MC/R600/flat.s diff --git a/llvm/docs/R600Usage.rst b/llvm/docs/R600Usage.rst index 093cdd7..9bd16f4 100644 --- a/llvm/docs/R600Usage.rst +++ b/llvm/docs/R600Usage.rst @@ -24,6 +24,11 @@ DS Instructions --------------- All DS instructions are supported. +FLAT Instructions +------------------ +These instructions are only present in the Sea Islands and Volcanic Islands +instruction set. All FLAT instructions are supported for these architectures + MUBUF Instructions ------------------ All non-atomic MUBUF instructions are supported. diff --git a/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp index 95025a6..02a6360 100644 --- a/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp @@ -376,6 +376,10 @@ public: OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands); OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); + OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands); + OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands); + void cvtFlat(MCInst &Inst, const OperandVector &Operands); + void cvtMubuf(MCInst &Inst, const OperandVector &Operands); OperandMatchResultTy parseOffset(OperandVector &Operands); OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands); @@ -1092,6 +1096,67 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { } //===----------------------------------------------------------------------===// +// flat +//===----------------------------------------------------------------------===// + +static const OptionalOperand FlatOptionalOps [] = { + {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr}, + {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, + {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr} +}; + +static const OptionalOperand FlatAtomicOptionalOps [] = { + {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr}, + {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr} +}; + +AMDGPUAsmParser::OperandMatchResultTy +AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) { + return parseOptionalOps(FlatOptionalOps, Operands); +} + +AMDGPUAsmParser::OperandMatchResultTy +AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) { + return parseOptionalOps(FlatAtomicOptionalOps, Operands); +} + +void AMDGPUAsmParser::cvtFlat(MCInst &Inst, + const OperandVector &Operands) { + std::map OptionalIdx; + + for (unsigned i = 1, e = Operands.size(); i != e; ++i) { + AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); + + // Add the register arguments + if (Op.isReg()) { + Op.addRegOperands(Inst, 1); + continue; + } + + // Handle 'glc' token which is sometimes hard-coded into the + // asm string. There are no MCInst operands for these. + if (Op.isToken()) + continue; + + // Handle optional arguments + OptionalIdx[Op.getImmTy()] = i; + + } + + // flat atomic instructions don't have a glc argument. + if (OptionalIdx.count(AMDGPUOperand::ImmTyGLC)) { + unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC]; + ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1); + } + + unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC]; + unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE]; + + ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1); + ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1); +} + +//===----------------------------------------------------------------------===// // mubuf //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/R600/CIInstructions.td b/llvm/lib/Target/R600/CIInstructions.td index 08c468d..2f5fdbe 100644 --- a/llvm/lib/Target/R600/CIInstructions.td +++ b/llvm/lib/Target/R600/CIInstructions.td @@ -41,89 +41,86 @@ defm V_LOG_LEGACY_F32 : VOP1Inst , "v_log_legacy_f32", defm V_EXP_LEGACY_F32 : VOP1Inst , "v_exp_legacy_f32", VOP_F32_F32 >; -} // End SubtargetPredicate = isCIVI //===----------------------------------------------------------------------===// // Flat Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasFlatAddressSpace] in { -def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VGPR_32>; -def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VGPR_32>; -def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VGPR_32>; -def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VGPR_32>; -def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VGPR_32>; -def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>; -def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>; -def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>; - -def FLAT_STORE_BYTE : FLAT_Store_Helper < - 0x00000018, "flat_store_byte", VGPR_32 ->; - -def FLAT_STORE_SHORT : FLAT_Store_Helper < - 0x0000001a, "flat_store_short", VGPR_32 ->; - -def FLAT_STORE_DWORD : FLAT_Store_Helper < - 0x0000001c, "flat_store_dword", VGPR_32 ->; - +def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x8, "flat_load_ubyte", VGPR_32>; +def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x9, "flat_load_sbyte", VGPR_32>; +def FLAT_LOAD_USHORT : FLAT_Load_Helper <0xa, "flat_load_ushort", VGPR_32>; +def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0xb, "flat_load_sshort", VGPR_32>; +def FLAT_LOAD_DWORD : FLAT_Load_Helper <0xc, "flat_load_dword", VGPR_32>; +def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0xd, "flat_load_dwordx2", VReg_64>; +def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0xe, "flat_load_dwordx4", VReg_128>; +def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0xf, "flat_load_dwordx3", VReg_96>; +def FLAT_STORE_BYTE : FLAT_Store_Helper <0x18, "flat_store_byte", VGPR_32>; +def FLAT_STORE_SHORT : FLAT_Store_Helper <0x1a, "flat_store_short", VGPR_32>; +def FLAT_STORE_DWORD : FLAT_Store_Helper <0x1c, "flat_store_dword", VGPR_32>; def FLAT_STORE_DWORDX2 : FLAT_Store_Helper < - 0x0000001d, "flat_store_dwordx2", VReg_64 + 0x1d, "flat_store_dwordx2", VReg_64 >; - def FLAT_STORE_DWORDX4 : FLAT_Store_Helper < - 0x0000001e, "flat_store_dwordx4", VReg_128 + 0x1e, "flat_store_dwordx4", VReg_128 >; - def FLAT_STORE_DWORDX3 : FLAT_Store_Helper < - 0x0000001e, "flat_store_dwordx3", VReg_96 + 0x1f, "flat_store_dwordx3", VReg_96 +>; +defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <0x30, "flat_atomic_swap", VGPR_32>; +defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC < + 0x31, "flat_atomic_cmpswap", VGPR_32, VReg_64 +>; +defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <0x32, "flat_atomic_add", VGPR_32>; +defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <0x33, "flat_atomic_sub", VGPR_32>; +defm FLAT_ATOMIC_RSUB : FLAT_ATOMIC <0x34, "flat_atomic_rsub", VGPR_32>; +defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <0x35, "flat_atomic_smin", VGPR_32>; +defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <0x36, "flat_atomic_umin", VGPR_32>; +defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <0x37, "flat_atomic_smax", VGPR_32>; +defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <0x38, "flat_atomic_umax", VGPR_32>; +defm FLAT_ATOMIC_AND : FLAT_ATOMIC <0x39, "flat_atomic_and", VGPR_32>; +defm FLAT_ATOMIC_OR : FLAT_ATOMIC <0x3a, "flat_atomic_or", VGPR_32>; +defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <0x3b, "flat_atomic_xor", VGPR_32>; +defm FLAT_ATOMIC_INC : FLAT_ATOMIC <0x3c, "flat_atomic_inc", VGPR_32>; +defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <0x3d, "flat_atomic_dec", VGPR_32>; +defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC < + 0x3e, "flat_atomic_fcmpswap", VGPR_32, VReg_64 +>; +defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <0x3f, "flat_atomic_fmin", VGPR_32>; +defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <0x40, "flat_atomic_fmax", VGPR_32>; +defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <0x50, "flat_atomic_swap_x2", VReg_64>; +defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_ATOMIC < + 0x51, "flat_atomic_cmpswap_x2", VReg_64, VReg_128 >; +defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <0x52, "flat_atomic_add_x2", VReg_64>; +defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <0x53, "flat_atomic_sub_x2", VReg_64>; +defm FLAT_ATOMIC_RSUB_X2 : FLAT_ATOMIC <0x54, "flat_atomic_rsub_x2", VReg_64>; +defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <0x55, "flat_atomic_smin_x2", VReg_64>; +defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <0x56, "flat_atomic_umin_x2", VReg_64>; +defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <0x57, "flat_atomic_smax_x2", VReg_64>; +defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <0x58, "flat_atomic_umax_x2", VReg_64>; +defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <0x59, "flat_atomic_and_x2", VReg_64>; +defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <0x5a, "flat_atomic_or_x2", VReg_64>; +defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <0x5b, "flat_atomic_xor_x2", VReg_64>; +defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <0x5c, "flat_atomic_inc_x2", VReg_64>; +defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <0x5d, "flat_atomic_dec_x2", VReg_64>; +defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC < + 0x5e, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128 +>; +defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <0x5f, "flat_atomic_fmin_x2", VReg_64>; +defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <0x60, "flat_atomic_fmax_x2", VReg_64>; -//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>; -//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>; -//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>; -//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>; -//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>; -//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>; -//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>; -//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>; -//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>; -//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>; -//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>; -//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>; -//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>; -//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>; -//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>; -//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>; -//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>; -//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>; -//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>; -//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>; -//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>; -//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>; -//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>; -//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>; -//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>; -//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>; -//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>; -//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>; -//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>; -//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>; -//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>; -//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>; -//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>; -//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>; +} // End SubtargetPredicate = isCIVI //===----------------------------------------------------------------------===// // Flat Patterns //===----------------------------------------------------------------------===// +let Predicates = [HasFlatAddressSpace] in { + class FLATLoad_Pattern : Pat <(vt (flat_ld i64:$ptr)), - (Instr_ADDR64 $ptr) + (Instr_ADDR64 $ptr, 0, 0, 0) >; def : FLATLoad_Pattern ; @@ -138,7 +135,7 @@ def : FLATLoad_Pattern ; class FLATStore_Pattern : Pat <(st vt:$value, i64:$ptr), - (Instr $value, $ptr) + (Instr $value, $ptr, 0, 0, 0) >; def : FLATStore_Pattern ; diff --git a/llvm/lib/Target/R600/SIInstrFormats.td b/llvm/lib/Target/R600/SIInstrFormats.td index 1409b1b..211666a 100644 --- a/llvm/lib/Target/R600/SIInstrFormats.td +++ b/llvm/lib/Target/R600/SIInstrFormats.td @@ -655,6 +655,7 @@ class FLAT op, dag outs, dag ins, string asm, list pattern> : let UseNamedOperandTable = 1; let hasSideEffects = 0; + let AsmMatchConverter = "cvtFlat"; let SchedRW = [WriteVMEM]; } diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 4fc2498..93e4ca7 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -390,27 +390,38 @@ class GDSBaseMatchClass : AsmOperandClass { def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">; def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">; -def GLCMatchClass : AsmOperandClass { - let Name = "GLC"; +class GLCBaseMatchClass : AsmOperandClass { + let Name = "GLC"#parser; let PredicateMethod = "isImm"; - let ParserMethod = "parseMubufOptionalOps"; + let ParserMethod = parser; let RenderMethod = "addImmOperands"; } -def SLCMatchClass : AsmOperandClass { - let Name = "SLC"; +def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">; +def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">; + +class SLCBaseMatchClass : AsmOperandClass { + let Name = "SLC"#parser; let PredicateMethod = "isImm"; - let ParserMethod = "parseMubufOptionalOps"; + let ParserMethod = parser; let RenderMethod = "addImmOperands"; } -def TFEMatchClass : AsmOperandClass { - let Name = "TFE"; +def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">; +def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">; +def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">; + +class TFEBaseMatchClass : AsmOperandClass { + let Name = "TFE"#parser; let PredicateMethod = "isImm"; - let ParserMethod = "parseMubufOptionalOps"; + let ParserMethod = parser; let RenderMethod = "addImmOperands"; } +def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">; +def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">; +def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">; + def OModMatchClass : AsmOperandClass { let Name = "OMod"; let PredicateMethod = "isImm"; @@ -463,19 +474,32 @@ def gds : gds_base ; def gds01 : gds_base ; -def glc : Operand { +class glc_base : Operand { let PrintMethod = "printGLC"; - let ParserMatchClass = GLCMatchClass; + let ParserMatchClass = mc; } -def slc : Operand { + +def glc : glc_base ; +def glc_flat : glc_base ; + +class slc_base : Operand { let PrintMethod = "printSLC"; - let ParserMatchClass = SLCMatchClass; + let ParserMatchClass = mc; } -def tfe : Operand { + +def slc : slc_base ; +def slc_flat : slc_base ; +def slc_flat_atomic : slc_base ; + +class tfe_base : Operand { let PrintMethod = "printTFE"; - let ParserMatchClass = TFEMatchClass; + let ParserMatchClass = mc; } +def tfe : tfe_base ; +def tfe_flat : tfe_base ; +def tfe_flat_atomic : tfe_base ; + def omod : Operand { let PrintMethod = "printOModSI"; let ParserMatchClass = OModMatchClass; @@ -2335,30 +2359,48 @@ multiclass MUBUF_Store_Helper op, string asm, RegisterClass regClass> : FLAT { - let glc = 0; - let slc = 0; - let tfe = 0; + (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe), + asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> { let data = 0; let mayLoad = 1; } class FLAT_Store_Helper op, string name, RegisterClass vdataClass> : - FLAT { let mayLoad = 0; let mayStore = 1; // Encoding - let glc = 0; - let slc = 0; - let tfe = 0; let vdst = 0; } +multiclass FLAT_ATOMIC op, string name, RegisterClass vdst_rc, + RegisterClass data_rc = vdst_rc> { + + let mayLoad = 1, mayStore = 1 in { + def "" : FLAT , + AtomicNoRet { + let glc = 0; + let vdst = 0; + } + + def _RTN : FLAT , + AtomicNoRet { + let glc = 1; + } + } +} + class MIMG_Mask { string Op = op; int Channels = channels; diff --git a/llvm/test/CodeGen/R600/flat-address-space.ll b/llvm/test/CodeGen/R600/flat-address-space.ll index 425d67d..8ceca07 100644 --- a/llvm/test/CodeGen/R600/flat-address-space.ll +++ b/llvm/test/CodeGen/R600/flat-address-space.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: {{^}}branch_use_flat_i32: -; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH] +; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} ; CHECK: s_endpgm define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { entry: diff --git a/llvm/test/MC/R600/flat.s b/llvm/test/MC/R600/flat.s new file mode 100644 index 0000000..adad29a --- /dev/null +++ b/llvm/test/MC/R600/flat.s @@ -0,0 +1,477 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI +// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI + +// FIXME: These instructions give an 'invalid operand' error on SI and should +// instead be reporting an 'instruction not supported' error. + +// XUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=NOVI +// XUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI +// XUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI + +//===----------------------------------------------------------------------===// +// Operands +//===----------------------------------------------------------------------===// + +flat_load_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_store_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +// FIXME: For atomic instructions, glc must be placed immediately following +// the data regiser. These forms aren't currently supported: +// flat_atomic_add v1, v[3:4], v5 slc glc +// flat_atomic_add v1, v[3:4], v5 slc glc tfe +// flat_atomic_add v1, v[3:4], v5 slc tfe glc +// flat_atomic_add v1, v[3:4], v5 tfe glc +// flat_atomic_add v[3:4], v5 tfe glc +// flat_atomic_add v1, v[3:4], v5 tfe glc slc +// flat_atomic_add v1, v[3:4], v5 tfe slc glc + +flat_atomic_add v1 v[3:4], v5 glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_add v1 v[3:4], v5 glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v1 v[3:4], v5 glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v1 v[3:4], v5 glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v[3:4], v5 slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_add v[3:4], v5 slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00] + +flat_atomic_add v[3:4], v5 tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +flat_load_ubyte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x20,0xdc,0x03,0x00,0x00,0x01] + +flat_load_sbyte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x24,0xdc,0x03,0x00,0x00,0x01] + +flat_load_ushort v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x28,0xdc,0x03,0x00,0x00,0x01] + +flat_load_sshort v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x2c,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dwordx2 v[1:2], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x34,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dwordx4 v[5:8], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x38,0xdc,0x03,0x00,0x00,0x05] + +flat_load_dwordx3 v[5:7], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x3c,0xdc,0x03,0x00,0x00,0x05] + +flat_store_byte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_byte v1, v[3:4] ; encoding: [0x00,0x00,0x60,0xdc,0x03,0x01,0x00,0x00] + +flat_store_short v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_short v1, v[3:4] ; encoding: [0x00,0x00,0x68,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dwordx2 v[1:2], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x74,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dwordx4 v[5:8], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00] + +flat_store_dwordx3 v[5:7], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_swap v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0xc0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_swap v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_cmpswap v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xc4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_cmpswap v1, v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xc5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_add v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_add v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_sub v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0xcc,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_sub v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xcd,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_smin v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0xd4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_smin v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_umin v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0xd8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_umin v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_smax v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0xdc,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_smax v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xdd,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_umax v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0xe0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_umax v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_and v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0xe4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_and v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_or v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0xe8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_or v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_xor v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0xec,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_xor v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xed,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_inc v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0xf0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_inc v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_dec v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0xf4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_dec v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_swap_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x40,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x41,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_cmpswap_x2 v[3:4], v[5:8] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x44,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x45,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_add_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x48,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x49,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_sub_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x4c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x4d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_smin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x54,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x55,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_umin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x58,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_smax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x5c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x5d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_umax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x60,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x61,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_and_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x64,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x65,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_or_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x68,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x69,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_xor_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x6c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x6d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_inc_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x70,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x71,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_dec_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x74,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x75,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_fcmpswap_x2 v[3:4], v[5:8] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fcmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x78,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x79,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x7c,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x7d,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x80,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x81,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU -- 2.7.4