From 128fdfa23f269d62aa51edf9c85ce34688b6c188 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Tue, 3 Jul 2018 16:01:27 +0000 Subject: [PATCH] [AArch64][SVE] Asm: Support for FP Complex ADD/MLA. The variants added in this patch are: - Predicated Complex floating point ADD with rotate, e.g. fcadd z0.h, p0/m, z0.h, z1.h, #90 - Predicated Complex floating point MLA with rotate, e.g. fcmla z0.h, p0/m, z1.h, z2.h, #180 - Unpredicated Complex floating point MLA with rotate (indexed operand), e.g. fcmla z0.h, p0/m, z1.h, z2.h[0], #180 Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D48824 llvm-svn: 336210 --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 3 + .../AArch64/AsmParser/AArch64AsmParser.cpp | 10 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 105 ++++++++++++++++++ llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s | 37 ++++++ llvm/test/MC/AArch64/SVE/fcadd.s | 44 ++++++++ llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s | 52 +++++++++ llvm/test/MC/AArch64/SVE/fcmla.s | 104 +++++++++++++++++ 7 files changed, 351 insertions(+), 4 deletions(-) create mode 100644 llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/fcadd.s create mode 100644 llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/fcmla.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index ee075d0eaa96..2b0d3e71f1f4 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -56,7 +56,10 @@ let Predicates = [HasSVE] in { defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>; + defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; + defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; + defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">; defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">; // Splat immediate (unpredicated) diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 61a8205efd5e..ece1dbe7987e 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1044,14 +1044,16 @@ public: } template - bool isComplexRotation() const { - if (!isImm()) return false; + DiagnosticPredicate isComplexRotation() const { + if (!isImm()) return DiagnosticPredicateTy::NoMatch; const MCConstantExpr *CE = dyn_cast(getImm()); - if (!CE) return false; + if (!CE) return DiagnosticPredicateTy::NoMatch; uint64_t Value = CE->getValue(); - return (Value % Angle == Remainder && Value <= 270); + if (Value % Angle == Remainder && Value <= 270) + return DiagnosticPredicateTy::Match; + return DiagnosticPredicateTy::NearMatch; } template bool isGPR64() const { diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 27b1885a4a0a..9a7be1516543 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -821,6 +821,111 @@ multiclass sve_fp_fmul_by_indexed_elem { } } +//===----------------------------------------------------------------------===// +// SVE Floating Point Complex Multiply-Add Group +//===----------------------------------------------------------------------===// + +class sve_fp_fcmla sz, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm, + complexrotateop:$imm), + asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm", + "", []>, Sched<[]> { + bits<5> Zda; + bits<3> Pg; + bits<5> Zn; + bits<5> Zm; + bits<2> imm; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21} = 0; + let Inst{20-16} = Zm; + let Inst{15} = 0; + let Inst{14-13} = imm; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; +} + +multiclass sve_fp_fcmla { + def _H : sve_fp_fcmla<0b01, asm, ZPR16>; + def _S : sve_fp_fcmla<0b10, asm, ZPR32>; + def _D : sve_fp_fcmla<0b11, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE Floating Point Complex Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +class sve_fp_fcmla_by_indexed_elem sz, string asm, + ZPRRegOp zprty, + ZPRRegOp zprty2, Operand itype> +: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop, + complexrotateop:$imm), + asm, "\t$Zda, $Zn, $Zm$iop, $imm", + "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<2> imm; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-12} = 0b0001; + let Inst{11-10} = imm; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; +} + +multiclass sve_fp_fcmla_by_indexed_elem { + def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> { + bits<4> Zm; + bits<1> iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// +// SVE Floating Point Complex Addition Group +//===----------------------------------------------------------------------===// + +class sve_fp_fcadd sz, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, + complexrotateopodd:$imm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zm; + bits<3> Pg; + bit imm; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21-17} = 0; + let Inst{16} = imm; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_fp_fcadd { + def _H : sve_fp_fcadd<0b01, asm, ZPR16>; + def _S : sve_fp_fcadd<0b10, asm, ZPR32>; + def _D : sve_fp_fcadd<0b11, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Stack Allocation Group //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s b/llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s new file mode 100644 index 000000000000..b9e54d0d0b40 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fcadd z0.d, p2/m, z1.d, z2.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fcadd z0.d, p2/m, z1.d, z2.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Restricted predicate out of range. + +fcadd z0.d, p8/m, z0.d, z1.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcadd z0.d, p8/m, z0.d, z1.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +fcadd z0.d, p0/m, z0.d, z1.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcadd z0.d, p0/m, z0.d, z1.d, #180 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #180 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcadd z0.d, p0/m, z0.d, z1.d, #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/fcadd.s b/llvm/test/MC/AArch64/SVE/fcadd.s new file mode 100644 index 000000000000..5e8c8324c773 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fcadd.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fcadd z0.h, p0/m, z0.h, z0.h, #90 +// CHECK-INST: fcadd z0.h, p0/m, z0.h, z0.h, #90 +// CHECK-ENCODING: [0x00,0x80,0x40,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 40 64 + +fcadd z0.s, p0/m, z0.s, z0.s, #90 +// CHECK-INST: fcadd z0.s, p0/m, z0.s, z0.s, #90 +// CHECK-ENCODING: [0x00,0x80,0x80,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 80 64 + +fcadd z0.d, p0/m, z0.d, z0.d, #90 +// CHECK-INST: fcadd z0.d, p0/m, z0.d, z0.d, #90 +// CHECK-ENCODING: [0x00,0x80,0xc0,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 c0 64 + +fcadd z31.h, p7/m, z31.h, z31.h, #270 +// CHECK-INST: fcadd z31.h, p7/m, z31.h, z31.h, #270 +// CHECK-ENCODING: [0xff,0x9f,0x41,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 9f 41 64 + +fcadd z31.s, p7/m, z31.s, z31.s, #270 +// CHECK-INST: fcadd z31.s, p7/m, z31.s, z31.s, #270 +// CHECK-ENCODING: [0xff,0x9f,0x81,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 9f 81 64 + +fcadd z31.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcadd z31.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xff,0x9f,0xc1,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 9f c1 64 diff --git a/llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s b/llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s new file mode 100644 index 000000000000..560b15f3de90 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s @@ -0,0 +1,52 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Restricted predicate out of range. + +fcmla z0.d, p8/m, z1.d, z2.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcmla z0.d, p8/m, z1.d, z2.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +fcmla z0.d, p0/m, z1.d, z2.d, #360 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: fcmla z0.d, p0/m, z1.d, z2.d, #360 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcmla z0.d, p0/m, z1.d, z2.d, #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: fcmla z0.d, p0/m, z1.d, z2.d, #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Index out of bounds or invalid for element size + +fcmla z0.h, z1.h, z2.h[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fcmla z0.h, z1.h, z2.h[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcmla z0.h, z1.h, z2.h[4], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fcmla z0.h, z1.h, z2.h[4], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcmla z0.s, z1.s, z2.s[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fcmla z0.s, z1.s, z2.s[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcmla z0.s, z1.s, z2.s[2], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fcmla z0.s, z1.s, z2.s[2], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcmla z0.d, z1.d, z2.d[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/fcmla.s b/llvm/test/MC/AArch64/SVE/fcmla.s new file mode 100644 index 000000000000..3a0954e7c8ef --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fcmla.s @@ -0,0 +1,104 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fcmla z0.h, p0/m, z0.h, z0.h, #0 +// CHECK-INST: fcmla z0.h, p0/m, z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0x00,0x40,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 00 40 64 + +fcmla z0.s, p0/m, z0.s, z0.s, #0 +// CHECK-INST: fcmla z0.s, p0/m, z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0x00,0x80,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 00 80 64 + +fcmla z0.d, p0/m, z0.d, z0.d, #0 +// CHECK-INST: fcmla z0.d, p0/m, z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0x00,0xc0,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 00 c0 64 + +fcmla z0.h, p0/m, z1.h, z2.h, #90 +// CHECK-INST: fcmla z0.h, p0/m, z1.h, z2.h, #90 +// CHECK-ENCODING: [0x20,0x20,0x42,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 42 64 + +fcmla z0.s, p0/m, z1.s, z2.s, #90 +// CHECK-INST: fcmla z0.s, p0/m, z1.s, z2.s, #90 +// CHECK-ENCODING: [0x20,0x20,0x82,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 82 64 + +fcmla z0.d, p0/m, z1.d, z2.d, #90 +// CHECK-INST: fcmla z0.d, p0/m, z1.d, z2.d, #90 +// CHECK-ENCODING: [0x20,0x20,0xc2,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 c2 64 + +fcmla z29.h, p7/m, z30.h, z31.h, #180 +// CHECK-INST: fcmla z29.h, p7/m, z30.h, z31.h, #180 +// CHECK-ENCODING: [0xdd,0x5f,0x5f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: dd 5f 5f 64 + +fcmla z29.s, p7/m, z30.s, z31.s, #180 +// CHECK-INST: fcmla z29.s, p7/m, z30.s, z31.s, #180 +// CHECK-ENCODING: [0xdd,0x5f,0x9f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: dd 5f 9f 64 + +fcmla z29.d, p7/m, z30.d, z31.d, #180 +// CHECK-INST: fcmla z29.d, p7/m, z30.d, z31.d, #180 +// CHECK-ENCODING: [0xdd,0x5f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: dd 5f df 64 + +fcmla z31.h, p7/m, z31.h, z31.h, #270 +// CHECK-INST: fcmla z31.h, p7/m, z31.h, z31.h, #270 +// CHECK-ENCODING: [0xff,0x7f,0x5f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 5f 64 + +fcmla z31.s, p7/m, z31.s, z31.s, #270 +// CHECK-INST: fcmla z31.s, p7/m, z31.s, z31.s, #270 +// CHECK-ENCODING: [0xff,0x7f,0x9f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 9f 64 + +fcmla z31.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcmla z31.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xff,0x7f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f df 64 + +fcmla z0.h, z0.h, z0.h[0], #0 +// CHECK-INST: fcmla z0.h, z0.h, z0.h[0], #0 +// CHECK-ENCODING: [0x00,0x10,0xa0,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 10 a0 64 + +fcmla z23.s, z13.s, z8.s[0], #270 +// CHECK-INST: fcmla z23.s, z13.s, z8.s[0], #270 +// CHECK-ENCODING: [0xb7,0x1d,0xe8,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 1d e8 64 + +fcmla z31.h, z31.h, z7.h[3], #270 +// CHECK-INST: fcmla z31.h, z31.h, z7.h[3], #270 +// CHECK-ENCODING: [0xff,0x1f,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f bf 64 + +fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-ENCODING: [0x55,0x15,0xf5,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 15 f5 64 -- 2.34.1