From 122b8666921c6864f532c8a0b654b3ba7a6fb012 Mon Sep 17 00:00:00 2001 From: rsandifo Date: Fri, 25 Jun 2004 06:59:03 +0000 Subject: [PATCH] * config/mips/mips.c (reg_or_const_float_1_operand): Reimplement in terms of const_float_1_operand. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@83640 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/mips/mips.c | 19 +++---------------- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c99ac82..80c7a80 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-06-25 Richard Sandiford + * config/mips/mips.c (reg_or_const_float_1_operand): Reimplement + in terms of const_float_1_operand. + +2004-06-25 Richard Sandiford + PR target/16144 * config/mips/mips.md (divsf, divdf): Don't FAIL if the first operand is 1.0; force it into a register instead. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index f481c4b..fe3e66d 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1428,26 +1428,13 @@ reg_or_0_operand (rtx op, enum machine_mode mode) } } -/* Accept a register or the floating point constant 1 in the appropriate mode. */ +/* Accept a register or the floating point constant 1 in the + appropriate mode. */ int reg_or_const_float_1_operand (rtx op, enum machine_mode mode) { - REAL_VALUE_TYPE d; - - switch (GET_CODE (op)) - { - case CONST_DOUBLE: - if (mode != GET_MODE (op) - || (mode != DFmode && mode != SFmode)) - return 0; - - REAL_VALUE_FROM_CONST_DOUBLE (d, op); - return REAL_VALUES_EQUAL (d, dconst1); - - default: - return register_operand (op, mode); - } + return const_float_1_operand (op, mode) || register_operand (op, mode); } /* Accept the floating point constant 1 in the appropriate mode. */ -- 2.7.4