From 1218a2e39fded75543d1dea04b8ed50e59ac6cdd Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Sat, 25 Sep 2021 20:20:52 -0400 Subject: [PATCH] drm/amdgpu: make software ring functions reuseable for newer VCN MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Software ring will be supported only from VCN4 Signed-off-by: Leo Liu Reviewed-by: James Zhu Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 23 +++++++++++------------ drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h | 12 ++++++++++++ 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 19cdad3..930d3bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1728,8 +1728,8 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) } } -static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, - u64 seq, uint32_t flags) +void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, uint32_t flags) { WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); @@ -1740,15 +1740,13 @@ static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); } -static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) +void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); } -static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, - struct amdgpu_job *job, - struct amdgpu_ib *ib, - uint32_t flags) +void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, + struct amdgpu_ib *ib, uint32_t flags) { uint32_t vmid = AMDGPU_JOB_GET_VMID(job); @@ -1759,8 +1757,8 @@ static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ib->length_dw); } -static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, - uint32_t val, uint32_t mask) +void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask) { amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); amdgpu_ring_write(ring, reg << 2); @@ -1768,8 +1766,8 @@ static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_ amdgpu_ring_write(ring, val); } -static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, - uint32_t vmid, uint64_t pd_addr) +void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, + uint32_t vmid, uint64_t pd_addr) { struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; uint32_t data0, data1, mask; @@ -1783,7 +1781,8 @@ static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); } -static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) +void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val) { amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); amdgpu_ring_write(ring, reg << 2); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h index 3168358..7a6655d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h @@ -26,4 +26,16 @@ extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block; +void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, uint32_t flags); +void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring); +void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, + struct amdgpu_ib *ib, uint32_t flags); +void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask); +void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, + uint32_t vmid, uint64_t pd_addr); +void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val); + #endif /* __VCN_V3_0_H__ */ -- 2.7.4