From 120070973425d785734837c06800dba3da4d1ac3 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 6 Mar 2020 16:30:48 +0800 Subject: [PATCH] RISC-V: Fix testsuite regression due to recent IRA changes. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/riscv/pr93304.c | 7 +++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 09d5973..6c9206a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-06 Kito Cheng + + * gcc.target/riscv/pr93304.c: Update expected output and comment. + 2020-03-06 Delia Burduv * gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c: New test. diff --git a/gcc/testsuite/gcc.target/riscv/pr93304.c b/gcc/testsuite/gcc.target/riscv/pr93304.c index f771e48..248f205 100644 --- a/gcc/testsuite/gcc.target/riscv/pr93304.c +++ b/gcc/testsuite/gcc.target/riscv/pr93304.c @@ -13,7 +13,6 @@ foo (void) /* Register rename will try to use registers from the lower register regradless of the REG_ALLOC_ORDER. - In theory, t0-t6 should not used in such small program if regrename - not executed incorrectly, because a5-a0 has higher priority in - REG_ALLOC_ORDER. */ -/* { dg-final { scan-assembler-not "t\[0-6\]" } } */ + In theory, t2 should not used in such small program if regrename + not executed incorrectly, because t0-a2 should be enough. */ +/* { dg-final { scan-assembler-not "t2" } } */ -- 2.7.4