From 118b8675c5946c38d5a914a63fe0c2f6f61d9eba Mon Sep 17 00:00:00 2001 From: Stefan Pintilie Date: Fri, 13 Apr 2018 19:49:58 +0000 Subject: [PATCH] [Power9] Add the TLS store instructions to the Power 9 model The Power 9 scheduler model should now include the TLS instructions. We can now, once again, mark the model as complete. From now on, if instructions are added to Power 9 but are not added to the model the build should produce an error. Hopefully that will alert the developer who is adding new instructions that they should also be added to the scheulder model. llvm-svn: 330060 --- llvm/lib/Target/PowerPC/P9InstrResources.td | 2 +- llvm/lib/Target/PowerPC/PPCScheduleP9.td | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td index d87fbd1..c4a3a63 100644 --- a/llvm/lib/Target/PowerPC/P9InstrResources.td +++ b/llvm/lib/Target/PowerPC/P9InstrResources.td @@ -894,7 +894,7 @@ def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C], (instregex "(D|X)FSTORE(f32|f64)$"), (instregex "ST(W|H|D)BRX$"), (instregex "ST(B|H|D)(8)?$"), - (instregex "ST(B|W|H|D)(CI)?X(8)?$"), + (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?$"), STIWX, SLBIEG, STMW, diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td index 6db2a79..dbebc75 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -33,7 +33,7 @@ def P9Model : SchedMachineModel { // A dispatch group is 6 instructions. let LoopMicroOpBufferSize = 60; - let CompleteModel = 0; + let CompleteModel = 1; // Do not support QPX (Quad Processing eXtension) on Power 9. let UnsupportedFeatures = [HasQPX]; -- 2.7.4