From 118366441744984cfa0994b0c87bb147a2269428 Mon Sep 17 00:00:00 2001 From: meissner Date: Thu, 14 Apr 2016 23:21:30 +0000 Subject: [PATCH] [gcc] 2016-04-14 Michael Meissner PR target/70669 * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add direct move handlers for KFmode. Change TFmode handlers test from FLOAT128_IEEE_P to FLOAT128_VECTOR_P. [gcc/testsuite] 2016-04-14 Michael Meissner PR target/70669 * gcc.target/powerpc/pr70669.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234995 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.c | 30 +++++++++++++++++++++++++----- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.target/powerpc/pr70669.c | 22 ++++++++++++++++++++++ 4 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr70669.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f5f320..f6fdeff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-04-14 Michael Meissner + + PR target/70669 + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add + direct move handlers for KFmode. Change TFmode handlers test from + FLOAT128_IEEE_P to FLOAT128_VECTOR_P. + 2016-04-14 Jakub Jelinek PR c++/70594 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c63fa06..1d0076c 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3132,8 +3132,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load; reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; - reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store; - reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load; reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; @@ -3141,7 +3139,13 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; - if (FLOAT128_IEEE_P (TFmode)) + if (FLOAT128_VECTOR_P (KFmode)) + { + reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store; + reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load; + } + + if (FLOAT128_VECTOR_P (TFmode)) { reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store; reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load; @@ -3182,6 +3186,18 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi; reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi; reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf; + + if (FLOAT128_VECTOR_P (KFmode)) + { + reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf; + reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf; + } + + if (FLOAT128_VECTOR_P (TFmode)) + { + reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf; + reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf; + } } } else @@ -3200,8 +3216,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; - reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store; - reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load; reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; @@ -3209,6 +3223,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; + if (FLOAT128_VECTOR_P (KFmode)) + { + reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store; + reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load; + } + if (FLOAT128_IEEE_P (TFmode)) { reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4b68cb3..4131b9f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2016-04-14 Michael Meissner + PR target/70669 + * gcc.target/powerpc/pr70669.c: New test. + PR target/70640 * gcc.target/powerpc/pr70640.c: Fix test so it correctly works on a power7 system that does not have an assembler that supports diff --git a/gcc/testsuite/gcc.target/powerpc/pr70669.c b/gcc/testsuite/gcc.target/powerpc/pr70669.c new file mode 100644 index 0000000..8054102 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70669.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O2 -mcpu=power8 -mfloat128" } */ + +#ifndef TYPE +#define TYPE __float128 +#endif + +void foo (TYPE *p, TYPE *q) +{ + TYPE r = *q; +#ifndef NO_ASM + __asm__ (" # %0" : "+r" (r)); +#endif + *p = r; +} + +/* { dg-final { scan-assembler "mfvsrd" } } */ +/* { dg-final { scan-assembler "mtvsrd" } } */ +/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 1 } } */ -- 2.7.4