From 112830f1a03d9365349d1ad300451ea5c535ab4d Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Mon, 28 Nov 2022 17:29:45 +0900 Subject: [PATCH] asahi: Pass through layer alignment flag to the hardware Signed-off-by: Asahi Lina Part-of: --- src/asahi/lib/cmdbuf.xml | 4 ++-- src/gallium/drivers/asahi/agx_state.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml index 2bc27e3..754ce05 100644 --- a/src/asahi/lib/cmdbuf.xml +++ b/src/asahi/lib/cmdbuf.xml @@ -213,7 +213,7 @@ array texture (with a layered framebuffer) --> - + @@ -251,7 +251,7 @@ - + diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index 1fbb336..bd6d012 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -556,7 +556,7 @@ agx_pack_texture(void *out, struct agx_resource *rsrc, assert(rsrc->layout.tiling == AIL_TILING_TWIDDLED || rsrc->layout.tiling == AIL_TILING_TWIDDLED_COMPRESSED); - cfg.unk_tiled = true; + cfg.page_aligned_layers = rsrc->layout.page_aligned_layers; } } } @@ -887,7 +887,7 @@ agx_batch_upload_pbe(struct agx_batch *batch, unsigned rt) cfg.stride = ail_get_linear_stride_B(&tex->layout, level) - 4; cfg.levels = 1; } else { - cfg.unk_tiled = true; + cfg.page_aligned_layers = tex->layout.page_aligned_layers; cfg.levels = tex->base.last_level + 1; } }; -- 2.7.4