From 10cb538eae234992e655e6022deb5d266abf2b9c Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Tue, 8 Dec 1998 07:40:07 +0000 Subject: [PATCH] i960 cgen simulator support. * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. start-sanitize-cygnus (CLEANFILES): Add stamp-i960. (I960_DEPS): Define. (i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960): New makefile rules. end-sanitize-cygnus (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. * Makefile.in: Rebuilt. * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, i960-dis.c to ta. * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. --- opcodes/.Sanitize | 4 + opcodes/ChangeLog | 17 + opcodes/i960c-asm.c | 739 +++++++ opcodes/i960c-dis.c | 782 +++++++ opcodes/i960c-opc.c | 5829 +++++++++++++++++++++++++++++++++++++++++++++++++++ opcodes/i960c-opc.h | 454 ++++ 6 files changed, 7825 insertions(+) create mode 100644 opcodes/i960c-asm.c create mode 100644 opcodes/i960c-dis.c create mode 100644 opcodes/i960c-opc.c create mode 100644 opcodes/i960c-opc.h diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize index 944a219..49b8a02 100644 --- a/opcodes/.Sanitize +++ b/opcodes/.Sanitize @@ -88,6 +88,10 @@ h8500-opc.h hppa-dis.c i386-dis.c i960-dis.c +i960c-asm.c +i960c-dis.c +i960c-opc.c +i960c-opc.h m32r-asm.c m32r-dis.c m32r-opc.c diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6acd6ec..77f0ab2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,20 @@ +1998-12-07 James E Wilson + + * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. + (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. +start-sanitize-cygnus + (CLEANFILES): Add stamp-i960. + (I960_DEPS): Define. + (i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960): + New makefile rules. +end-sanitize-cygnus + (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. + * Makefile.in: Rebuilt. + * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, + i960-dis.c to ta. + * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. + start-sanitize-fr30 Mon Dec 7 14:33:44 1998 Dave Brolley diff --git a/opcodes/i960c-asm.c b/opcodes/i960c-asm.c new file mode 100644 index 0000000..10a0e5c --- /dev/null +++ b/opcodes/i960c-asm.c @@ -0,0 +1,739 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS USED TO GENERATE i960c-asm.c. + +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "i960c-opc.h" +#include "opintl.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +#undef INLINE +#ifdef __GNUC__ +#define INLINE __inline__ +#else +#define INLINE +#endif + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * parse_insn_normal + PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, + const char **, CGEN_FIELDS *)); +static const char * insert_insn_normal + PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* -- assembler routines inserted here */ + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. +*/ + +const char * +i960_cgen_parse_operand (od, opindex, strp, fields) + CGEN_OPCODE_DESC od; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg; + + switch (opindex) + { + case I960_OPERAND_SRC1 : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src1); + break; + case I960_OPERAND_SRC2 : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src2); + break; + case I960_OPERAND_DST : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst); + break; + case I960_OPERAND_LIT1 : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT1, &fields->f_src1); + break; + case I960_OPERAND_LIT2 : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT2, &fields->f_src2); + break; + case I960_OPERAND_ST_SRC : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst); + break; + case I960_OPERAND_ABASE : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_abase); + break; + case I960_OPERAND_OFFSET : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OFFSET, &fields->f_offset); + break; + case I960_OPERAND_SCALE : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_SCALE, &fields->f_scale); + break; + case I960_OPERAND_INDEX : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_index); + break; + case I960_OPERAND_OPTDISP : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OPTDISP, &fields->f_optdisp); + break; + case I960_OPERAND_BR_SRC1 : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src1); + break; + case I960_OPERAND_BR_SRC2 : + errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src2); + break; + case I960_OPERAND_BR_DISP : + { + bfd_vma value; + errmsg = cgen_parse_address (od, strp, I960_OPERAND_BR_DISP, 0, NULL, & value); + fields->f_br_disp = value; + } + break; + case I960_OPERAND_BR_LIT1 : + errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_BR_LIT1, &fields->f_br_src1); + break; + case I960_OPERAND_CTRL_DISP : + { + bfd_vma value; + errmsg = cgen_parse_address (od, strp, I960_OPERAND_CTRL_DISP, 0, NULL, & value); + fields->f_ctrl_disp = value; + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. +*/ + +const char * +i960_cgen_insert_operand (od, opindex, fields, buffer, pc) + CGEN_OPCODE_DESC od; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const char * errmsg; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case I960_OPERAND_SRC1 : + errmsg = insert_normal (od, fields->f_src1, 0|(1<f_src2, 0|(1<f_srcdst, 0|(1<f_src1, 0|(1<f_src2, 0|(1<f_srcdst, 0|(1<f_abase, 0|(1<f_offset, 0|(1<f_scale, 0|(1<f_index, 0|(1<f_optdisp, 0|(1<f_br_src1, 0|(1<f_br_src2, 0|(1<f_br_disp; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (od, value, 0|(1<f_br_src1, 0|(1<f_ctrl_disp; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (od, value, 0|(1<> 16; + bfd_putb16 (x, bufp + 1); + } + else + { + bfd_putl16 (x, bufp); + bufp[2] = x >> 16; + } + break; + case 32: + if (big_p) + bfd_putb32 (x, bufp); + else + bfd_putl32 (x, bufp); + break; + default : + abort (); + } +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (od, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_OPCODE_DESC od; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ +#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; +#endif + + /* Ensure VALUE will fit. */ + if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0) + { + unsigned long maxval = mask; + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = word_length - (start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (od, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. +*/ + +static const char * +parse_insn_normal (od, insn, strp, fields) + CGEN_OPCODE_DESC od; + const CGEN_INSN * insn; + const char ** strp; + CGEN_FIELDS * fields; +{ + const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); + const char * str = *strp; + const char * errmsg; + const char * p; + const unsigned char * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && tolower (*p) == tolower (*str)) + ++p, ++str; + + if (* p || (* str && !isspace (* str))) + return _("unrecognized instruction"); + + CGEN_INIT_PARSE (od); + cgen_init_parse_operand (od); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + if (*str == CGEN_SYNTAX_CHAR (* syn)) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (* syn == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else + { + /* Syntax char didn't match. Can't be this insn. */ + /* FIXME: would like to return something like + "expected char `c'" */ + return _("syntax error"); + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = i960_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == '\0') + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (isspace (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order + (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is + recorded in host byte order, otherwise BUFFER is an array of bytes and the + value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (od, insn, fields, buffer, pc) + CGEN_OPCODE_DESC od; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const unsigned char * syn; + + CGEN_INIT_INSERT (od); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + *buffer = value; + +#else + + cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE, + CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = i960_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. */ + +const CGEN_INSN * +i960_cgen_assemble_insn (od, str, fields, buf, errmsg) + CGEN_OPCODE_DESC od; + const char * str; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buf; + char ** errmsg; +{ + const char * start; + CGEN_INSN_LIST * ilist; + + /* Skip leading white space. */ + while (isspace (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (od, str); + + /* Keep looking until we find a match. */ + + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + +#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ + /* Is this insn supported by the selected cpu? */ + if (! i960_cgen_insn_supported (od, insn)) + continue; +#endif + + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields)) + { + /* ??? 0 is passed for `pc' */ + if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL) + continue; + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + /* Try the next entry. */ + } + + /* FIXME: We can return a better error message than this. + Need to track why it failed and pick the right one. */ + { + static char errbuf[100]; + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +i960_cgen_asm_hash_keywords (od, opvals) + CGEN_OPCODE_DESC od; + CGEN_KEYWORD * opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! i960_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (od, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/i960c-dis.c b/opcodes/i960c-dis.c new file mode 100644 index 0000000..4985fec --- /dev/null +++ b/opcodes/i960c-dis.c @@ -0,0 +1,782 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS USED TO GENERATE i960c-dis.c. + +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "i960c-opc.h" +#include "opintl.h" + +#undef INLINE +#ifdef __GNUC__ +#define INLINE __inline__ +#else +#define INLINE +#endif + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static int extract_normal + PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static void print_normal + PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static int extract_insn_normal + PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +static void print_insn_normal + PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma, + disassemble_info *, char *, int)); +static int default_print_insn + PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *)); + +/* -- disassembler routines inserted here */ + +/* Main entry point for operand extraction. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +int +i960_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) + CGEN_OPCODE_DESC od; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + int length; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case I960_OPERAND_SRC1 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_src1); + break; + case I960_OPERAND_SRC2 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_src2); + break; + case I960_OPERAND_DST : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_srcdst); + break; + case I960_OPERAND_LIT1 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_src1); + break; + case I960_OPERAND_LIT2 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_src2); + break; + case I960_OPERAND_ST_SRC : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_srcdst); + break; + case I960_OPERAND_ABASE : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_abase); + break; + case I960_OPERAND_OFFSET : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_offset); + break; + case I960_OPERAND_SCALE : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_scale); + break; + case I960_OPERAND_INDEX : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_index); + break; + case I960_OPERAND_OPTDISP : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_optdisp); + break; + case I960_OPERAND_BR_SRC1 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_br_src1); + break; + case I960_OPERAND_BR_SRC2 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_br_src2); + break; + case I960_OPERAND_BR_DISP : + { + long value; + length = extract_normal (od, ex_info, insn_value, 0|(1<f_br_disp = value; + } + break; + case I960_OPERAND_BR_LIT1 : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_br_src1); + break; + case I960_OPERAND_CTRL_DISP : + { + long value; + length = extract_normal (od, ex_info, insn_value, 0|(1<f_ctrl_disp = value; + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +/* Main entry point for printing operands. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +void +i960_cgen_print_operand (od, opindex, info, fields, attrs, pc, length) + CGEN_OPCODE_DESC od; + int opindex; + disassemble_info * info; + CGEN_FIELDS * fields; + void const * attrs; + bfd_vma pc; + int length; +{ + switch (opindex) + { + case I960_OPERAND_SRC1 : + print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_src1, 0|(1<f_src2, 0|(1<f_srcdst, 0|(1<f_src1, 0|(1<f_src2, 0|(1<f_srcdst, 0|(1<f_abase, 0|(1<f_offset, 0|(1<f_scale, 0|(1<f_index, 0|(1<f_optdisp, 0|(1<f_br_src1, 0|(1<f_br_src2, 0|(1<f_br_disp, 0|(1<f_br_src1, 0|(1<f_ctrl_disp, 0|(1<dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static INLINE long +extract_1 (od, ex_info, start, length, word_length, bufp, pc) + CGEN_OPCODE_DESC od; + CGEN_EXTRACT_INFO *ex_info; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc; +{ + unsigned long x,mask; + int shift; + int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; + + switch (word_length) + { + case 8: + x = *bufp; + break; + case 16: + if (big_p) + x = bfd_getb16 (bufp); + else + x = bfd_getl16 (bufp); + break; + case 24: + /* ??? This may need reworking as these cases don't necessarily + want the first byte and the last two bytes handled like this. */ + if (big_p) + x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); + else + x = bfd_getl16 (bufp) | (bufp[2] << 16); + break; + case 32: + if (big_p) + x = bfd_getb32 (bufp); + else + x = bfd_getl32 (bufp); + break; + default : + abort (); + } + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return (x >> shift) & mask; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `UNSIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_OPCODE_DESC od; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + bfd_vma pc; + long *valuep; +{ + CGEN_INSN_INT value; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ +#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; +#endif + + /* Does the value reside in INSN_VALUE? */ + + if (word_offset == 0) + { + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((start + 1) - length); + else + value = insn_value >> (word_length - (start + length)); + value &= mask; + /* sign extend? */ + if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) + && (value & (1L << (length - 1)))) + value |= ~mask; + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (od, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + *valuep = value; + + return 1; +} + +/* Default print handler. */ + +static void +print_normal (od, dis_info, value, attrs, pc, length) + CGEN_OPCODE_DESC od; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "%ld", value); +} + +/* Default address handler. */ + +static void +print_address (od, dis_info, value, attrs, pc, length) + CGEN_OPCODE_DESC od; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); + else + (*info->fprintf_func) (info->stream, "%ld", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (od, dis_info, keyword_table, value, attrs) + CGEN_OPCODE_DESC od; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn extractor. + + INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (od, insn, ex_info, insn_value, fields, pc) + CGEN_OPCODE_DESC od; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const unsigned char *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (od); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = i960_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (od, dis_info, insn, fields, pc, length) + CGEN_OPCODE_DESC od; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const unsigned char *syn; + + CGEN_INIT_PRINT (od); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + i960_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (od, pc, info, buf, buflen) + CGEN_OPCODE_DESC od; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + unsigned long insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + + ex_info.dis_info = info; + ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1; + ex_info.insn_bytes = buf; + + switch (buflen) + { + case 1: + insn_value = buf[0]; + break; + case 2: + insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); + break; + case 4: + insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); + break; + default: + abort (); + } + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + +#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ + /* Supported by this cpu? */ + if (! i960_cgen_insn_supported (od, insn)) + continue; +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + if ((insn_value & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value, + &fields, pc); + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (od, pc, info) + CGEN_OPCODE_DESC od; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int status; + + /* Read the base part of the insn. */ + + status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +int +print_insn_i960 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + int length; + static CGEN_OPCODE_DESC od = 0; + int mach = info->mach; + int big_p = info->endian == BFD_ENDIAN_BIG; + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! od) + { + od = i960_cgen_opcode_open (mach, + big_p ? + CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + i960_cgen_init_dis (od); + } + /* If we've switched cpu's, re-initialize. */ + /* ??? Perhaps we should use BFD_ENDIAN. */ + else if (mach != CGEN_OPCODE_MACH (od) + || (CGEN_OPCODE_ENDIAN (od) + != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE))) + { + cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (od, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return CGEN_DEFAULT_INSN_SIZE; +} diff --git a/opcodes/i960c-opc.c b/opcodes/i960c-opc.c new file mode 100644 index 0000000..e8b4c01 --- /dev/null +++ b/opcodes/i960c-opc.c @@ -0,0 +1,5829 @@ +/* Generic opcode table support for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS USED TO GENERATE i960c-opc.c. + +Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "symcat.h" +#include "i960c-opc.h" +#include "opintl.h" + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Look up instruction INSN_VALUE and extract its fields. + INSN, if non-null, is the insn table entry. + Otherwise INSN_VALUE is examined to compute it. + LENGTH is the bit length of INSN_VALUE if known, otherwise 0. + 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. + If INSN != NULL, LENGTH must be valid. + ALIAS_P is non-zero if alias insns are to be included in the search. + + The result is a pointer to the insn table entry, or NULL if the instruction + wasn't recognized. */ + +const CGEN_INSN * +i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p) + CGEN_OPCODE_DESC od; + const CGEN_INSN *insn; + CGEN_INSN_BYTES insn_value; + int length; + CGEN_FIELDS *fields; + int alias_p; +{ + unsigned char buf[CGEN_MAX_INSN_SIZE]; + unsigned char *bufp; + CGEN_INSN_INT base_insn; +#if CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *info = NULL; +#else + CGEN_EXTRACT_INFO ex_info; + CGEN_EXTRACT_INFO *info = &ex_info; +#endif + +#if CGEN_INT_INSN_P + cgen_put_insn_value (od, buf, length, insn_value); + bufp = buf; + base_insn = insn_value; /*???*/ +#else + ex_info.dis_info = NULL; + ex_info.insn_bytes = insn_value; + ex_info.valid = -1; + base_insn = cgen_get_insn_value (od, buf, length); + bufp = insn_value; +#endif + + if (!insn) + { + const CGEN_INSN_LIST *insn_list; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn); + while (insn_list != NULL) + { + insn = insn_list->insn; + + if (alias_p + || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) + { + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the + extract handler. */ + if ((base_insn & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* ??? 0 is passed for `pc' */ + int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, + base_insn, fields, + (bfd_vma) 0); + if (elength > 0) + { + /* sanity check */ + if (length != 0 && length != elength) + abort (); + return insn; + } + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + } + else + { + /* Sanity check: can't pass an alias insn if ! alias_p. */ + if (! alias_p + && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) + abort (); + /* Sanity check: length must be correct. */ + if (length != CGEN_INSN_BITSIZE (insn)) + abort (); + + /* ??? 0 is passed for `pc' */ + length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields, + (bfd_vma) 0); + /* Sanity check: must succeed. + Could relax this later if it ever proves useful. */ + if (length == 0) + abort (); + return insn; + } + + return NULL; +} + +/* Fill in the operand instances used by INSN whose operands are FIELDS. + INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled + in. */ + +void +i960_cgen_get_insn_operands (od, insn, fields, indices) + CGEN_OPCODE_DESC od; + const CGEN_INSN * insn; + const CGEN_FIELDS * fields; + int *indices; +{ + const CGEN_OPERAND_INSTANCE *opinst; + int i; + + for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); + opinst != NULL + && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; + ++i, ++opinst) + { + const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst); + if (op == NULL) + indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); + else + indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), + fields); + } +} + +/* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS + isn't known. + The INSN, INSN_VALUE, and LENGTH arguments are passed to + i960_cgen_lookup_insn unchanged. + + The result is the insn table entry or NULL if the instruction wasn't + recognized. */ + +const CGEN_INSN * +i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices) + CGEN_OPCODE_DESC od; + const CGEN_INSN *insn; + CGEN_INSN_BYTES insn_value; + int length; + int *indices; +{ + CGEN_FIELDS fields; + + /* Pass non-zero for ALIAS_P only if INSN != NULL. + If INSN == NULL, we want a real insn. */ + insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields, + insn != NULL); + if (! insn) + return NULL; + + i960_cgen_get_insn_operands (od, insn, &fields, indices); + return insn; +} +/* Attributes. */ + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "i960_ka_sa", MACH_I960_KA_SA }, + { "i960_ca", MACH_I960_CA }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] = +{ + { "CACHE-ADDR", NULL }, + { "PC", NULL }, + { "PROFILE", NULL }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] = +{ + { "ABS-ADDR", NULL }, + { "NEGATIVE", NULL }, + { "PCREL-ADDR", NULL }, + { "RELAX", NULL }, + { "RELOC", NULL }, + { "SEM-ONLY", NULL }, + { "SIGN-OPT", NULL }, + { "UNSIGNED", NULL }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] = +{ + { "ALIAS", NULL }, + { "COND-CTI", NULL }, + { "DELAY-SLOT", NULL }, + { "NO-DIS", NULL }, + { "RELAX", NULL }, + { "RELAXABLE", NULL }, + { "SKIP-CTI", NULL }, + { "UNCOND-CTI", NULL }, + { "VIRTUAL", NULL }, + { 0, 0 } +}; + +CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = +{ + { "fp", 31 }, + { "sp", 1 }, + { "r0", 0 }, + { "r1", 1 }, + { "r2", 2 }, + { "r3", 3 }, + { "r4", 4 }, + { "r5", 5 }, + { "r6", 6 }, + { "r7", 7 }, + { "r8", 8 }, + { "r9", 9 }, + { "r10", 10 }, + { "r11", 11 }, + { "r12", 12 }, + { "r13", 13 }, + { "r14", 14 }, + { "r15", 15 }, + { "g0", 16 }, + { "g1", 17 }, + { "g2", 18 }, + { "g3", 19 }, + { "g4", 20 }, + { "g5", 21 }, + { "g6", 22 }, + { "g7", 23 }, + { "g8", 24 }, + { "g9", 25 }, + { "g10", 26 }, + { "g11", 27 }, + { "g12", 28 }, + { "g13", 29 }, + { "g14", 30 }, + { "g15", 31 } +}; + +CGEN_KEYWORD i960_cgen_opval_h_gr = +{ + & i960_cgen_opval_h_gr_entries[0], + 34 +}; + +CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = +{ + { "cc", 0 } +}; + +CGEN_KEYWORD i960_cgen_opval_h_cc = +{ + & i960_cgen_opval_h_cc_entries[0], + 1 +}; + + +/* The hardware table. */ + +#define HW_ENT(n) i960_cgen_hw_entries[n] +static const CGEN_HW_ENTRY i960_cgen_hw_entries[] = +{ + { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<f_src1; + break; + case I960_OPERAND_SRC2 : + value = fields->f_src2; + break; + case I960_OPERAND_DST : + value = fields->f_srcdst; + break; + case I960_OPERAND_LIT1 : + value = fields->f_src1; + break; + case I960_OPERAND_LIT2 : + value = fields->f_src2; + break; + case I960_OPERAND_ST_SRC : + value = fields->f_srcdst; + break; + case I960_OPERAND_ABASE : + value = fields->f_abase; + break; + case I960_OPERAND_OFFSET : + value = fields->f_offset; + break; + case I960_OPERAND_SCALE : + value = fields->f_scale; + break; + case I960_OPERAND_INDEX : + value = fields->f_index; + break; + case I960_OPERAND_OPTDISP : + value = fields->f_optdisp; + break; + case I960_OPERAND_BR_SRC1 : + value = fields->f_br_src1; + break; + case I960_OPERAND_BR_SRC2 : + value = fields->f_br_src2; + break; + case I960_OPERAND_BR_DISP : + value = fields->f_br_disp; + break; + case I960_OPERAND_BR_LIT1 : + value = fields->f_br_src1; + break; + case I960_OPERAND_CTRL_DISP : + value = fields->f_ctrl_disp; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +i960_cgen_get_vma_operand (opindex, fields) + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case I960_OPERAND_SRC1 : + value = fields->f_src1; + break; + case I960_OPERAND_SRC2 : + value = fields->f_src2; + break; + case I960_OPERAND_DST : + value = fields->f_srcdst; + break; + case I960_OPERAND_LIT1 : + value = fields->f_src1; + break; + case I960_OPERAND_LIT2 : + value = fields->f_src2; + break; + case I960_OPERAND_ST_SRC : + value = fields->f_srcdst; + break; + case I960_OPERAND_ABASE : + value = fields->f_abase; + break; + case I960_OPERAND_OFFSET : + value = fields->f_offset; + break; + case I960_OPERAND_SCALE : + value = fields->f_scale; + break; + case I960_OPERAND_INDEX : + value = fields->f_index; + break; + case I960_OPERAND_OPTDISP : + value = fields->f_optdisp; + break; + case I960_OPERAND_BR_SRC1 : + value = fields->f_br_src1; + break; + case I960_OPERAND_BR_SRC2 : + value = fields->f_br_src2; + break; + case I960_OPERAND_BR_DISP : + value = fields->f_br_disp; + break; + case I960_OPERAND_BR_LIT1 : + value = fields->f_br_src1; + break; + case I960_OPERAND_CTRL_DISP : + value = fields->f_ctrl_disp; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +i960_cgen_set_int_operand (opindex, fields, value) + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case I960_OPERAND_SRC1 : + fields->f_src1 = value; + break; + case I960_OPERAND_SRC2 : + fields->f_src2 = value; + break; + case I960_OPERAND_DST : + fields->f_srcdst = value; + break; + case I960_OPERAND_LIT1 : + fields->f_src1 = value; + break; + case I960_OPERAND_LIT2 : + fields->f_src2 = value; + break; + case I960_OPERAND_ST_SRC : + fields->f_srcdst = value; + break; + case I960_OPERAND_ABASE : + fields->f_abase = value; + break; + case I960_OPERAND_OFFSET : + fields->f_offset = value; + break; + case I960_OPERAND_SCALE : + fields->f_scale = value; + break; + case I960_OPERAND_INDEX : + fields->f_index = value; + break; + case I960_OPERAND_OPTDISP : + fields->f_optdisp = value; + break; + case I960_OPERAND_BR_SRC1 : + fields->f_br_src1 = value; + break; + case I960_OPERAND_BR_SRC2 : + fields->f_br_src2 = value; + break; + case I960_OPERAND_BR_DISP : + fields->f_br_disp = value; + break; + case I960_OPERAND_BR_LIT1 : + fields->f_br_src1 = value; + break; + case I960_OPERAND_CTRL_DISP : + fields->f_ctrl_disp = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +i960_cgen_set_vma_operand (opindex, fields, value) + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case I960_OPERAND_SRC1 : + fields->f_src1 = value; + break; + case I960_OPERAND_SRC2 : + fields->f_src2 = value; + break; + case I960_OPERAND_DST : + fields->f_srcdst = value; + break; + case I960_OPERAND_LIT1 : + fields->f_src1 = value; + break; + case I960_OPERAND_LIT2 : + fields->f_src2 = value; + break; + case I960_OPERAND_ST_SRC : + fields->f_srcdst = value; + break; + case I960_OPERAND_ABASE : + fields->f_abase = value; + break; + case I960_OPERAND_OFFSET : + fields->f_offset = value; + break; + case I960_OPERAND_SCALE : + fields->f_scale = value; + break; + case I960_OPERAND_INDEX : + fields->f_index = value; + break; + case I960_OPERAND_OPTDISP : + fields->f_optdisp = value; + break; + case I960_OPERAND_BR_SRC1 : + fields->f_br_src1 = value; + break; + case I960_OPERAND_BR_SRC2 : + fields->f_br_src2 = value; + break; + case I960_OPERAND_BR_DISP : + fields->f_br_disp = value; + break; + case I960_OPERAND_BR_LIT1 : + fields->f_br_src1 = value; + break; + case I960_OPERAND_CTRL_DISP : + fields->f_ctrl_disp = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + diff --git a/opcodes/i960c-opc.h b/opcodes/i960c-opc.h new file mode 100644 index 0000000..7b62ced --- /dev/null +++ b/opcodes/i960c-opc.h @@ -0,0 +1,454 @@ +/* Instruction description for i960. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef I960_OPC_H +#define I960_OPC_H + +#define CGEN_ARCH i960 + +/* Given symbol S, return i960_cgen_. */ +#define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s) + +/* Selected cpu families. */ +#define HAVE_CPU_I960BASE + +#define CGEN_INSN_LSB0_P 0 +#define CGEN_WORD_BITSIZE 32 +#define CGEN_DEFAULT_INSN_BITSIZE 32 +#define CGEN_BASE_INSN_BITSIZE 32 +#define CGEN_MIN_INSN_BITSIZE 32 +#define CGEN_MAX_INSN_BITSIZE 64 +#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) +#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) +#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) +#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) +#define CGEN_INT_INSN_P 0 + +/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS +/* Maximum number of operands any insn or macro-insn has. */ +#define CGEN_MAX_INSN_OPERANDS 16 + +/* Maximum number of fields in an instruction. */ +#define CGEN_MAX_IFMT_OPERANDS 9 + +/* Enums. */ + +/* Enum declaration for insn opcode enums. */ +typedef enum insn_opcode { + OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03 + , OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07 + , OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B + , OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F + , OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13 + , OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17 + , OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B + , OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F + , OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23 + , OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27 + , OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B + , OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F + , OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33 + , OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37 + , OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B + , OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F + , OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43 + , OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47 + , OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B + , OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F + , OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53 + , OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57 + , OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B + , OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F + , OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63 + , OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67 + , OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B + , OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F + , OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73 + , OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77 + , OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B + , OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F + , OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83 + , OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87 + , OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B + , OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F + , OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93 + , OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97 + , OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B + , OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F + , OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3 + , OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7 + , OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB + , OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF + , OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3 + , OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7 + , OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB + , OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF + , OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3 + , OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7 + , OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB + , OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF + , OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3 + , OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7 + , OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB + , OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF + , OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3 + , OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7 + , OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB + , OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF + , OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3 + , OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7 + , OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB + , OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF +} INSN_OPCODE; + +/* Enum declaration for insn opcode2 enums. */ +typedef enum insn_opcode2 { + OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3 + , OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7 + , OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B + , OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F +} INSN_OPCODE2; + +/* Enum declaration for insn m3 enums. */ +typedef enum insn_m3 { + M3_0, M3_1 +} INSN_M3; + +/* Enum declaration for insn m3 enums. */ +typedef enum insn_m2 { + M2_0, M2_1 +} INSN_M2; + +/* Enum declaration for insn m1 enums. */ +typedef enum insn_m1 { + M1_0, M1_1 +} INSN_M1; + +/* Enum declaration for insn zero enums. */ +typedef enum insn_zero { + ZERO_0 +} INSN_ZERO; + +/* Enum declaration for insn mode a enums. */ +typedef enum insn_modea { + MODEA_OFFSET, MODEA_INDIRECT_OFFSET +} INSN_MODEA; + +/* Enum declaration for insn zero a enums. */ +typedef enum insn_zeroa { + ZEROA_0 +} INSN_ZEROA; + +/* Enum declaration for insn mode b enums. */ +typedef enum insn_modeb { + MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3 + , MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX + , MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11 + , MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP +} INSN_MODEB; + +/* Enum declaration for insn zero b enums. */ +typedef enum insn_zerob { + ZEROB_0 +} INSN_ZEROB; + +/* Enum declaration for insn branch m1 enums. */ +typedef enum insn_br_m1 { + BR_M1_0, BR_M1_1 +} INSN_BR_M1; + +/* Enum declaration for insn branch zero enums. */ +typedef enum insn_br_zero { + BR_ZERO_0 +} INSN_BR_ZERO; + +/* Enum declaration for insn ctrl zero enums. */ +typedef enum insn_ctrl_zero { + CTRL_ZERO_0 +} INSN_CTRL_ZERO; + +/* Enum declaration for general registers. */ +typedef enum h_gr { + H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1 + , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 + , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 + , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 + , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17 + , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21 + , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25 + , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29 + , H_GR_G14 = 30, H_GR_G15 = 31 +} H_GR; + +/* Enum declaration for condition code. */ +typedef enum h_cc { + H_CC_CC +} H_CC; + +/* Enum declaration for i960 operand types. */ +typedef enum cgen_operand_type { + I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST + , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE + , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP + , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1 + , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Non-boolean attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX +} MACH_ATTR; + +/* Number of architecture variants. */ +#define MAX_MACHS ((int) MACH_MAX) + +/* Number of operands types. */ +#define MAX_OPERANDS ((int) I960_OPERAND_MAX) + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 54 + +/* Hardware, operand and instruction attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw. */ +#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR) + +/* Hardware, operand and instruction attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RELOC, CGEN_IFLD_RESERVED + , CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld. */ +#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR) + +/* Enum declaration for i960 ifield types. */ +typedef enum ifield_type { + I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2 + , I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2 + , I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA + , I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE + , I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1 + , I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO + , I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) I960_F_MAX) + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX + , CGEN_OPERAND_RELOC, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand. */ +#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR) + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS + , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI + , CGEN_INSN_VIRTUAL +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn. */ +#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS) + +/* Enum declaration for i960 instruction types. */ +typedef enum cgen_insn_type { + I960_INSN_INVALID, I960_INSN_MULO, I960_INSN_MULO1, I960_INSN_MULO2 + , I960_INSN_MULO3, I960_INSN_REMO, I960_INSN_REMO1, I960_INSN_REMO2 + , I960_INSN_REMO3, I960_INSN_DIVO, I960_INSN_DIVO1, I960_INSN_DIVO2 + , I960_INSN_DIVO3, I960_INSN_REMI, I960_INSN_REMI1, I960_INSN_REMI2 + , I960_INSN_REMI3, I960_INSN_DIVI, I960_INSN_DIVI1, I960_INSN_DIVI2 + , I960_INSN_DIVI3, I960_INSN_ADDO, I960_INSN_ADDO1, I960_INSN_ADDO2 + , I960_INSN_ADDO3, I960_INSN_SUBO, I960_INSN_SUBO1, I960_INSN_SUBO2 + , I960_INSN_SUBO3, I960_INSN_NOTBIT, I960_INSN_NOTBIT1, I960_INSN_NOTBIT2 + , I960_INSN_NOTBIT3, I960_INSN_AND, I960_INSN_AND1, I960_INSN_AND2 + , I960_INSN_AND3, I960_INSN_ANDNOT, I960_INSN_ANDNOT1, I960_INSN_ANDNOT2 + , I960_INSN_ANDNOT3, I960_INSN_SETBIT, I960_INSN_SETBIT1, I960_INSN_SETBIT2 + , I960_INSN_SETBIT3, I960_INSN_NOTAND, I960_INSN_NOTAND1, I960_INSN_NOTAND2 + , I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2 + , I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2 + , I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2 + , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2 + , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2 + , I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2 + , I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2 + , I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2 + , I960_INSN_SHLI3, I960_INSN_SHRI, I960_INSN_SHRI1, I960_INSN_SHRI2 + , I960_INSN_SHRI3, I960_INSN_EMUL, I960_INSN_EMUL1, I960_INSN_EMUL2 + , I960_INSN_EMUL3, I960_INSN_MOV, I960_INSN_MOV1, I960_INSN_MOVL + , I960_INSN_MOVL1, I960_INSN_MOVT, I960_INSN_MOVT1, I960_INSN_MOVQ + , I960_INSN_MOVQ1, I960_INSN_MODPC, I960_INSN_MODAC, I960_INSN_LDA_OFFSET + , I960_INSN_LDA_INDIRECT_OFFSET, I960_INSN_LDA_INDIRECT, I960_INSN_LDA_INDIRECT_INDEX, I960_INSN_LDA_DISP + , I960_INSN_LDA_INDIRECT_DISP, I960_INSN_LDA_INDEX_DISP, I960_INSN_LDA_INDIRECT_INDEX_DISP, I960_INSN_LD_OFFSET + , I960_INSN_LD_INDIRECT_OFFSET, I960_INSN_LD_INDIRECT, I960_INSN_LD_INDIRECT_INDEX, I960_INSN_LD_DISP + , I960_INSN_LD_INDIRECT_DISP, I960_INSN_LD_INDEX_DISP, I960_INSN_LD_INDIRECT_INDEX_DISP, I960_INSN_LDOB_OFFSET + , I960_INSN_LDOB_INDIRECT_OFFSET, I960_INSN_LDOB_INDIRECT, I960_INSN_LDOB_INDIRECT_INDEX, I960_INSN_LDOB_DISP + , I960_INSN_LDOB_INDIRECT_DISP, I960_INSN_LDOB_INDEX_DISP, I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960_INSN_LDOS_OFFSET + , I960_INSN_LDOS_INDIRECT_OFFSET, I960_INSN_LDOS_INDIRECT, I960_INSN_LDOS_INDIRECT_INDEX, I960_INSN_LDOS_DISP + , I960_INSN_LDOS_INDIRECT_DISP, I960_INSN_LDOS_INDEX_DISP, I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960_INSN_LDIB_OFFSET + , I960_INSN_LDIB_INDIRECT_OFFSET, I960_INSN_LDIB_INDIRECT, I960_INSN_LDIB_INDIRECT_INDEX, I960_INSN_LDIB_DISP + , I960_INSN_LDIB_INDIRECT_DISP, I960_INSN_LDIB_INDEX_DISP, I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960_INSN_LDIS_OFFSET + , I960_INSN_LDIS_INDIRECT_OFFSET, I960_INSN_LDIS_INDIRECT, I960_INSN_LDIS_INDIRECT_INDEX, I960_INSN_LDIS_DISP + , I960_INSN_LDIS_INDIRECT_DISP, I960_INSN_LDIS_INDEX_DISP, I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960_INSN_LDL_OFFSET + , I960_INSN_LDL_INDIRECT_OFFSET, I960_INSN_LDL_INDIRECT, I960_INSN_LDL_INDIRECT_INDEX, I960_INSN_LDL_DISP + , I960_INSN_LDL_INDIRECT_DISP, I960_INSN_LDL_INDEX_DISP, I960_INSN_LDL_INDIRECT_INDEX_DISP, I960_INSN_LDT_OFFSET + , I960_INSN_LDT_INDIRECT_OFFSET, I960_INSN_LDT_INDIRECT, I960_INSN_LDT_INDIRECT_INDEX, I960_INSN_LDT_DISP + , I960_INSN_LDT_INDIRECT_DISP, I960_INSN_LDT_INDEX_DISP, I960_INSN_LDT_INDIRECT_INDEX_DISP, I960_INSN_LDQ_OFFSET + , I960_INSN_LDQ_INDIRECT_OFFSET, I960_INSN_LDQ_INDIRECT, I960_INSN_LDQ_INDIRECT_INDEX, I960_INSN_LDQ_DISP + , I960_INSN_LDQ_INDIRECT_DISP, I960_INSN_LDQ_INDEX_DISP, I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960_INSN_ST_OFFSET + , I960_INSN_ST_INDIRECT_OFFSET, I960_INSN_ST_INDIRECT, I960_INSN_ST_INDIRECT_INDEX, I960_INSN_ST_DISP + , I960_INSN_ST_INDIRECT_DISP, I960_INSN_ST_INDEX_DISP, I960_INSN_ST_INDIRECT_INDEX_DISP, I960_INSN_STOB_OFFSET + , I960_INSN_STOB_INDIRECT_OFFSET, I960_INSN_STOB_INDIRECT, I960_INSN_STOB_INDIRECT_INDEX, I960_INSN_STOB_DISP + , I960_INSN_STOB_INDIRECT_DISP, I960_INSN_STOB_INDEX_DISP, I960_INSN_STOB_INDIRECT_INDEX_DISP, I960_INSN_STOS_OFFSET + , I960_INSN_STOS_INDIRECT_OFFSET, I960_INSN_STOS_INDIRECT, I960_INSN_STOS_INDIRECT_INDEX, I960_INSN_STOS_DISP + , I960_INSN_STOS_INDIRECT_DISP, I960_INSN_STOS_INDEX_DISP, I960_INSN_STOS_INDIRECT_INDEX_DISP, I960_INSN_STL_OFFSET + , I960_INSN_STL_INDIRECT_OFFSET, I960_INSN_STL_INDIRECT, I960_INSN_STL_INDIRECT_INDEX, I960_INSN_STL_DISP + , I960_INSN_STL_INDIRECT_DISP, I960_INSN_STL_INDEX_DISP, I960_INSN_STL_INDIRECT_INDEX_DISP, I960_INSN_STT_OFFSET + , I960_INSN_STT_INDIRECT_OFFSET, I960_INSN_STT_INDIRECT, I960_INSN_STT_INDIRECT_INDEX, I960_INSN_STT_DISP + , I960_INSN_STT_INDIRECT_DISP, I960_INSN_STT_INDEX_DISP, I960_INSN_STT_INDIRECT_INDEX_DISP, I960_INSN_STQ_OFFSET + , I960_INSN_STQ_INDIRECT_OFFSET, I960_INSN_STQ_INDIRECT, I960_INSN_STQ_INDIRECT_INDEX, I960_INSN_STQ_DISP + , I960_INSN_STQ_INDIRECT_DISP, I960_INSN_STQ_INDEX_DISP, I960_INSN_STQ_INDIRECT_INDEX_DISP, I960_INSN_CMPOBE_REG + , I960_INSN_CMPOBE_LIT, I960_INSN_CMPOBNE_REG, I960_INSN_CMPOBNE_LIT, I960_INSN_CMPOBL_REG + , I960_INSN_CMPOBL_LIT, I960_INSN_CMPOBLE_REG, I960_INSN_CMPOBLE_LIT, I960_INSN_CMPOBG_REG + , I960_INSN_CMPOBG_LIT, I960_INSN_CMPOBGE_REG, I960_INSN_CMPOBGE_LIT, I960_INSN_CMPIBE_REG + , I960_INSN_CMPIBE_LIT, I960_INSN_CMPIBNE_REG, I960_INSN_CMPIBNE_LIT, I960_INSN_CMPIBL_REG + , I960_INSN_CMPIBL_LIT, I960_INSN_CMPIBLE_REG, I960_INSN_CMPIBLE_LIT, I960_INSN_CMPIBG_REG + , I960_INSN_CMPIBG_LIT, I960_INSN_CMPIBGE_REG, I960_INSN_CMPIBGE_LIT, I960_INSN_BBC_REG + , I960_INSN_BBC_LIT, I960_INSN_BBS_REG, I960_INSN_BBS_LIT, I960_INSN_CMPI + , I960_INSN_CMPI1, I960_INSN_CMPI2, I960_INSN_CMPI3, I960_INSN_CMPO + , I960_INSN_CMPO1, I960_INSN_CMPO2, I960_INSN_CMPO3, I960_INSN_TESTNO_REG + , I960_INSN_TESTG_REG, I960_INSN_TESTE_REG, I960_INSN_TESTGE_REG, I960_INSN_TESTL_REG + , I960_INSN_TESTNE_REG, I960_INSN_TESTLE_REG, I960_INSN_TESTO_REG, I960_INSN_BNO + , I960_INSN_BG, I960_INSN_BE, I960_INSN_BGE, I960_INSN_BL + , I960_INSN_BNE, I960_INSN_BLE, I960_INSN_BO, I960_INSN_B + , I960_INSN_BX_INDIRECT_OFFSET, I960_INSN_BX_INDIRECT, I960_INSN_BX_INDIRECT_INDEX, I960_INSN_BX_DISP + , I960_INSN_BX_INDIRECT_DISP, I960_INSN_CALLX_DISP, I960_INSN_CALLX_INDIRECT, I960_INSN_CALLX_INDIRECT_OFFSET + , I960_INSN_RET, I960_INSN_CALLS, I960_INSN_FMARK, I960_INSN_FLUSHREG + , I960_INSN_MAX +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID I960_INSN_INVALID +/* Total number of insns in table. */ +#define MAX_INSNS ((int) I960_INSN_MAX) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + long f_nil; + long f_opcode; + long f_srcdst; + long f_src2; + long f_m3; + long f_m2; + long f_m1; + long f_opcode2; + long f_zero; + long f_src1; + long f_abase; + long f_modea; + long f_zeroa; + long f_offset; + long f_modeb; + long f_scale; + long f_zerob; + long f_index; + long f_optdisp; + long f_br_src1; + long f_br_src2; + long f_br_m1; + long f_br_disp; + long f_br_zero; + long f_ctrl_disp; + long f_ctrl_zero; + int length; +}; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[]; +extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[]; + +/* Enum declaration for i960 hardware types. */ +typedef enum hw_type { + HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT + , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC + , HW_MAX +} HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Hardware decls. */ + +extern CGEN_KEYWORD i960_cgen_opval_h_gr; +extern CGEN_KEYWORD i960_cgen_opval_h_cc; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 256 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) ((unsigned char *) (buffer))[3] + +/* ??? Until cgen disassembler complete and functioning well, redirect back + to old disassembler. */ +#define CGEN_PRINT_INSN(od, pc, info) print_insn_i960_orig (pc, info) + +/* -- */ + + +#endif /* I960_OPC_H */ -- 2.7.4