From 1067ec90a591b26a0d6c9b298b1a894bb0a66836 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 3 Jan 2023 09:40:54 -0800 Subject: [PATCH] anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+ MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer and also it have different requirements of flush, so here doing this two changes at the same time. As no ANV_PIPE_INVALIDATE_BITS is set as parameter of anv_add_pending_pipe_bits(), genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one PIPELINE_CONTROL. BSpec: 44505 Signed-off-by: José Roberto de Souza Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5a6025a..3f20836 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -6347,6 +6347,30 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, } #endif +#if GFX_VER >= 12 + /* From Tigerlake PRM, Volume 2a, PIPELINE_SELECT: + * + * "Software must ensure Render Cache, Depth Cache and HDC Pipeline flush + * are flushed through a stalling PIPE_CONTROL command prior to + * programming of PIPELINE_SELECT command transitioning Pipeline Select + * from 3D to GPGPU/Media. + * Software must ensure HDC Pipeline flush and Generic Media State Clear + * is issued through a stalling PIPE_CONTROL command prior to programming + * of PIPELINE_SELECT command transitioning Pipeline Select from + * GPGPU/Media to 3D." + * + * Note: Issuing PIPE_CONTROL_MEDIA_STATE_CLEAR causes GPU hangs, probably + * because PIPE was not in MEDIA mode?! + */ + enum anv_pipe_bits bits = ANV_PIPE_CS_STALL_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT; + + if (cmd_buffer->state.current_pipeline == _3D) { + bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; + } + anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT"); +#else /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] * PIPELINE_SELECT [DevBWR+]": * @@ -6371,6 +6395,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, "flush and invalidate for PIPELINE_SELECT"); +#endif genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); genX(emit_pipeline_select)(&cmd_buffer->batch, pipeline); -- 2.7.4