From 10511a493e01d2ae46830e3b0f872cf733f940d8 Mon Sep 17 00:00:00 2001 From: Ranjeet Singh Date: Mon, 8 Jun 2015 21:32:16 +0000 Subject: [PATCH] [AArch64] AsmParser should be case insensitive about accepting vector register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353 --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 +- llvm/test/MC/AArch64/case-insen-reg-names.s | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/AArch64/case-insen-reg-names.s diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 41615b6ede08..063c053ffe8a 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1764,7 +1764,7 @@ static unsigned MatchRegisterName(StringRef Name); /// } static unsigned matchVectorRegName(StringRef Name) { - return StringSwitch(Name) + return StringSwitch(Name.lower()) .Case("v0", AArch64::Q0) .Case("v1", AArch64::Q1) .Case("v2", AArch64::Q2) diff --git a/llvm/test/MC/AArch64/case-insen-reg-names.s b/llvm/test/MC/AArch64/case-insen-reg-names.s new file mode 100644 index 000000000000..b31ab675a7e1 --- /dev/null +++ b/llvm/test/MC/AArch64/case-insen-reg-names.s @@ -0,0 +1,8 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s + +fadd v0.2d, v5.2d, v6.2d +fadd V0.2d, V5.2d, V6.2d +fadd v0.2d, V5.2d, v6.2d +// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e] +// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e] +// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e] -- 2.34.1