From 1012dc67697625081383f74803f27b6e7da4b6dd Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Mon, 5 Sep 2022 17:31:08 +0800 Subject: [PATCH] clk:starfive:Set pll2 default rate to 1188m Change pll2_out default rate from 1228.8m to 1188m. Signed-off-by: Xingyu Wu --- drivers/clk/starfive/clk-starfive-jh7110-pll.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h index b812b72..eb2511c 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-pll.h +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h @@ -13,7 +13,7 @@ * If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2 * frequency will be set the new rate during clock tree registering. */ -#define PLL2_DEFAULT_FREQ PLL2_FREQ_12288_VALUE +#define PLL2_DEFAULT_FREQ PLL2_FREQ_1188_VALUE #define PLL0_INDEX 0 #define PLL1_INDEX 1 -- 2.7.4