From 100b4f2e9f65565e3e3e484162c4474effc54be8 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 18 Jan 2016 21:29:37 +0000 Subject: [PATCH] MIPS: Remove remnants of 48-bit microMIPS instruction support The POOL48A major opcode was defined in early revisions of the 64-bit microMIPS ISA, has never been implemented, and was removed before the 64-bit microMIPS ISA specification[1] has been finalized. This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS 48-bit LI instruction"). References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of Major Opcode Field", p. 578 gas/ * config/tc-mips.c (micromips_insn_length): Remove the mention of 48-bit microMIPS instructions. gdb/ * mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS instruction support. (micromips_next_pc): Likewise. (micromips_scan_prologue): Likewise. (micromips_deal_with_atomic_sequence): Likewise. (micromips_stack_frame_destroyed_p): Likewise. (mips_breakpoint_from_pc): Likewise. opcodes/ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS instruction support. --- gas/ChangeLog | 5 +++++ gas/config/tc-mips.c | 6 ++---- gdb/ChangeLog | 10 ++++++++++ gdb/mips-tdep.c | 37 ++++--------------------------------- opcodes/ChangeLog | 5 +++++ opcodes/mips-dis.c | 36 +----------------------------------- 6 files changed, 27 insertions(+), 72 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 1c0e224..a905d6f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2016-01-18 Maciej W. Rozycki + + * config/tc-mips.c (micromips_insn_length): Remove the mention + of 48-bit microMIPS instructions. + 2016-01-18 Alan Modra * configure: Regenerate. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 859ddc6..d577774 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2089,10 +2089,8 @@ mips_lookup_ase (const char *name) } /* Return the length of a microMIPS instruction in bytes. If bits of - the mask beyond the low 16 are 0, then it is a 16-bit instruction. - Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f - major opcode) will require further modifications to the opcode - table. */ + the mask beyond the low 16 are 0, then it is a 16-bit instruction, + otherwise it is a 32-bit instruction. */ static inline unsigned int micromips_insn_length (const struct mips_opcode *mo) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index cfe889d..e534dcc 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,15 @@ 2016-01-18 Maciej W. Rozycki + * mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS + instruction support. + (micromips_next_pc): Likewise. + (micromips_scan_prologue): Likewise. + (micromips_deal_with_atomic_sequence): Likewise. + (micromips_stack_frame_destroyed_p): Likewise. + (mips_breakpoint_from_pc): Likewise. + +2016-01-18 Maciej W. Rozycki + * mips-tdep.c (micromips_insn_at_pc_has_delay_slot): Pass unshifted 16-bit microMIPS instruction word to `mips_insn_size'. diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index f787a6d..63c1560f 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -1518,10 +1518,8 @@ mips_insn_size (enum mips_isa isa, ULONGEST insn) switch (isa) { case ISA_MICROMIPS: - if (micromips_op (insn) == 0x1f) - return 3 * MIPS_INSN16_SIZE; - else if (((micromips_op (insn) & 0x4) == 0x4) - || ((micromips_op (insn) & 0x7) == 0x0)) + if ((micromips_op (insn) & 0x4) == 0x4 + || (micromips_op (insn) & 0x7) == 0x0) return 2 * MIPS_INSN16_SIZE; else return MIPS_INSN16_SIZE; @@ -1881,12 +1879,6 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) pc += MIPS_INSN16_SIZE; switch (mips_insn_size (ISA_MICROMIPS, insn)) { - /* 48-bit instructions. */ - case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ - /* No branch or jump instructions in this category. */ - pc += 2 * MIPS_INSN16_SIZE; - break; - /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: insn <<= 16; @@ -2993,13 +2985,6 @@ micromips_scan_prologue (struct gdbarch *gdbarch, loc += MIPS_INSN16_SIZE; switch (mips_insn_size (ISA_MICROMIPS, insn)) { - /* 48-bit instructions. */ - case 3 * MIPS_INSN16_SIZE: - /* No prologue instructions in this category. */ - this_non_prologue_insn = 1; - loc += 2 * MIPS_INSN16_SIZE; - break; - /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: insn <<= 16; @@ -4041,11 +4026,6 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, its destination address. */ switch (mips_insn_size (ISA_MICROMIPS, insn)) { - /* 48-bit instructions. */ - case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ - loc += 2 * MIPS_INSN16_SIZE; - break; - /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: switch (micromips_op (insn)) @@ -6769,11 +6749,6 @@ micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) loc += MIPS_INSN16_SIZE; switch (mips_insn_size (ISA_MICROMIPS, insn)) { - /* 48-bit instructions. */ - case 3 * MIPS_INSN16_SIZE: - /* No epilogue instructions in this category. */ - return 0; - /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: insn <<= 16; @@ -7122,9 +7097,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch, int size; insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err); - size = (err != 0 - ? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2 - ? 2 : 4)); + size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn); *pcptr = unmake_compact_addr (pc); *lenptr = size; return (size == 2) ? micromips16_big_breakpoint @@ -7174,9 +7147,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch, int size; insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err); - size = (err != 0 - ? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2 - ? 2 : 4)); + size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn); *pcptr = unmake_compact_addr (pc); *lenptr = size; return (size == 2) ? micromips16_little_breakpoint diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3260c89..8a6ea15 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-01-18 Maciej W. Rozycki + + * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS + instruction support. + 2016-01-17 Alan Modra * configure: Regenerate. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 470f2ad..e152876 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -2185,41 +2185,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) else insn = bfd_getl16 (buffer); - if ((insn & 0xfc00) == 0x7c00) - { - /* This is a 48-bit microMIPS instruction. */ - higher = insn; - - status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 2, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - higher = (higher << 16) | insn; - - status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 4, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); - - info->insn_type = dis_noninsn; - return 6; - } - else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) + if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) { /* This is a 32-bit microMIPS instruction. */ higher = insn; -- 2.7.4