From 0ff076ab581d83fba6a6f14c3c550c789699678c Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Thu, 8 Jan 2015 16:00:38 +0000 Subject: [PATCH] Use LLD and SCD instructions on mips64 (Cherry-pick commits 54d1da5, 22ca163 and part of 9b7cecb from 'master' branch.) --- src/atomic_ops/sysdeps/gcc/mips.h | 56 +++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h index 291da58..f25453b 100644 --- a/src/atomic_ops/sysdeps/gcc/mips.h +++ b/src/atomic_ops/sysdeps/gcc/mips.h @@ -15,7 +15,6 @@ * FIXME: This should probably make finer distinctions. SGI MIPS is * much more strongly ordered, and in fact closer to sequentially * consistent. This is really aimed at modern embedded implementations. - * It looks to me like this assumes a 32-bit ABI. -HB */ #include "../all_aligned_atomic_load_store.h" @@ -25,14 +24,24 @@ /* Data dependence does not imply read ordering. */ #define AO_NO_DD_ORDERING +#ifdef __mips64 +# define AO_MIPS_SET_ISA " .set mips3\n" +# define AO_MIPS_LL_1(args) " lld " args "\n" +# define AO_MIPS_SC(args) " scd " args "\n" +#else +# define AO_MIPS_SET_ISA " .set mips2\n" +# define AO_MIPS_LL_1(args) " ll " args "\n" +# define AO_MIPS_SC(args) " sc " args "\n" +# define AO_T_IS_INT +#endif + #ifdef AO_ICE9A1_LLSC_WAR /* ICE9 rev A1 chip (used in very few systems) is reported to */ /* have a low-frequency bug that causes LL to fail. */ /* To workaround, just issue the second 'LL'. */ -# define AO_MIPS_LL_FIX(args_str) \ - " ll " args_str "\n" +# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) AO_MIPS_LL_1(args) #else -# define AO_MIPS_LL_FIX(args_str) "" +# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) #endif AO_INLINE void @@ -40,7 +49,7 @@ AO_nop_full(void) { __asm__ __volatile__( " .set push \n" - " .set mips2 \n" + AO_MIPS_SET_ISA " .set noreorder \n" " .set nomacro \n" " sync \n" @@ -58,13 +67,13 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr) __asm__ __volatile__( " .set push\n" - " .set mips2\n" + AO_MIPS_SET_ISA " .set noreorder\n" " .set nomacro\n" - "1: ll %0, %2\n" - AO_MIPS_LL_FIX("%0, %2") + "1: " + AO_MIPS_LL("%0, %2") " addu %1, %0, %3\n" - " sc %1, %2\n" + AO_MIPS_SC("%1, %2") " beqz %1, 1b\n" " nop\n" " .set pop " @@ -83,13 +92,13 @@ AO_test_and_set(volatile AO_TS_t *addr) __asm__ __volatile__( " .set push\n" - " .set mips2\n" + AO_MIPS_SET_ISA " .set noreorder\n" " .set nomacro\n" - "1: ll %0, %2\n" - AO_MIPS_LL_FIX("%0, %2") + "1: " + AO_MIPS_LL("%0, %2") " move %1, %3\n" - " sc %1, %2\n" + AO_MIPS_SC("%1, %2") " beqz %1, 1b\n" " nop\n" " .set pop " @@ -112,14 +121,14 @@ AO_test_and_set(volatile AO_TS_t *addr) __asm__ __volatile__( " .set push \n" - " .set mips2 \n" + AO_MIPS_SET_ISA " .set noreorder \n" " .set nomacro \n" - "1: ll %0, %1 \n" - AO_MIPS_LL_FIX("%0, %1") + "1: " + AO_MIPS_LL("%0, %1") " bne %0, %4, 2f \n" " move %0, %3 \n" - " sc %0, %1 \n" + AO_MIPS_SC("%0, %1") " .set pop \n" " beqz %0, 1b \n" " li %2, 1 \n" @@ -140,14 +149,14 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) __asm__ __volatile__( " .set push\n" - " .set mips2\n" + AO_MIPS_SET_ISA " .set noreorder\n" " .set nomacro\n" - "1: ll %0, %2\n" - AO_MIPS_LL_FIX("%0, %2") + "1: " + AO_MIPS_LL("%0, %2") " bne %0, %4, 2f\n" " move %1, %3\n" - " sc %1, %2\n" + AO_MIPS_SC("%1, %2") " beqz %1, 1b\n" " nop\n" " .set pop\n" @@ -166,5 +175,6 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) /* generated automatically (and AO_int_... primitives are */ /* defined properly after the first generalization pass). */ -/* FIXME: 32-bit ABI is assumed. */ -#define AO_T_IS_INT +#undef AO_MIPS_LL_1 +#undef AO_MIPS_SC +#undef AO_MIPS_SET_ISA -- 2.7.4