From 0fde412140ddbf8153a02e4d153c44398e441134 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Thu, 5 Sep 2019 18:49:52 +0000
Subject: [PATCH] [X86] Enable BuildSDIVPow2 for i16.

We're able to use a 32-bit ADD and CMOV here and should work
well with our other i16->i32 promotion optimizations.

llvm-svn: 371107
---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  5 +++--
 llvm/test/CodeGen/X86/combine-sdiv.ll   | 16 ++++++++--------
 llvm/test/CodeGen/X86/combine-srem.ll   | 18 ++++++++----------
 3 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d7efb0a126dd..136d124ab4ba 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -20098,8 +20098,9 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
 
   // fold (sdiv X, pow2)
   EVT VT = N->getValueType(0);
-  // FIXME: Support i8/i16.
-  if ((VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64)))
+  // FIXME: Support i8.
+  if (VT != MVT::i16 && VT != MVT::i32 &&
+      !(Subtarget.is64Bit() && VT == MVT::i64))
     return SDValue();
 
   unsigned Lg2 = Divisor.countTrailingZeros();
diff --git a/llvm/test/CodeGen/X86/combine-sdiv.ll b/llvm/test/CodeGen/X86/combine-sdiv.ll
index 59e13e7cea4d..137e03228c0f 100644
--- a/llvm/test/CodeGen/X86/combine-sdiv.ll
+++ b/llvm/test/CodeGen/X86/combine-sdiv.ll
@@ -3168,10 +3168,10 @@ define i8 @combine_i8_sdiv_negpow2(i8 %x) {
 define i16 @combine_i16_sdiv_pow2(i16 %x) {
 ; CHECK-LABEL: combine_i16_sdiv_pow2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movswl %di, %eax
-; CHECK-NEXT:    shrl $27, %eax
-; CHECK-NEXT:    andl $15, %eax
-; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    leal 15(%rdi), %eax
+; CHECK-NEXT:    testw %di, %di
+; CHECK-NEXT:    cmovnsl %edi, %eax
 ; CHECK-NEXT:    cwtl
 ; CHECK-NEXT:    shrl $4, %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -3183,10 +3183,10 @@ define i16 @combine_i16_sdiv_pow2(i16 %x) {
 define i16 @combine_i16_sdiv_negpow2(i16 %x) {
 ; CHECK-LABEL: combine_i16_sdiv_negpow2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movswl %di, %eax
-; CHECK-NEXT:    shrl $23, %eax
-; CHECK-NEXT:    movzbl %al, %eax
-; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    leal 255(%rdi), %eax
+; CHECK-NEXT:    testw %di, %di
+; CHECK-NEXT:    cmovnsl %edi, %eax
 ; CHECK-NEXT:    cwtl
 ; CHECK-NEXT:    sarl $8, %eax
 ; CHECK-NEXT:    negl %eax
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index 4148e5b6d35c..b08bb5b4dbda 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -480,13 +480,12 @@ define i16 @combine_i16_srem_pow2(i16 %x) {
 ; CHECK-LABEL: combine_i16_srem_pow2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    movswl %ax, %ecx
-; CHECK-NEXT:    shrl $27, %ecx
-; CHECK-NEXT:    andl $15, %ecx
-; CHECK-NEXT:    addl %edi, %ecx
+; CHECK-NEXT:    leal 15(%rax), %ecx
+; CHECK-NEXT:    testw %ax, %ax
+; CHECK-NEXT:    cmovnsl %edi, %ecx
 ; CHECK-NEXT:    andl $-16, %ecx
 ; CHECK-NEXT:    subl %ecx, %eax
-; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $rax
 ; CHECK-NEXT:    retq
   %1 = srem i16 %x, 16
   ret i16 %1
@@ -496,13 +495,12 @@ define i16 @combine_i16_srem_negpow2(i16 %x) {
 ; CHECK-LABEL: combine_i16_srem_negpow2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    movswl %ax, %ecx
-; CHECK-NEXT:    shrl $23, %ecx
-; CHECK-NEXT:    movzbl %cl, %ecx
-; CHECK-NEXT:    addl %edi, %ecx
+; CHECK-NEXT:    leal 255(%rax), %ecx
+; CHECK-NEXT:    testw %ax, %ax
+; CHECK-NEXT:    cmovnsl %edi, %ecx
 ; CHECK-NEXT:    andl $-256, %ecx
 ; CHECK-NEXT:    subl %ecx, %eax
-; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $rax
 ; CHECK-NEXT:    retq
   %1 = srem i16 %x, -256
   ret i16 %1
-- 
2.34.1