From 0fc9113ac593e396d3b103bebb2713aac9d072ff Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 6 Apr 2018 15:37:28 +0200 Subject: [PATCH] radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpers Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 18 +++++++++--------- src/amd/vulkan/radv_device.c | 10 +++++----- src/amd/vulkan/radv_image.c | 14 +++++++------- src/amd/vulkan/radv_meta_clear.c | 12 ++++++------ src/amd/vulkan/radv_meta_copy.c | 4 ++-- src/amd/vulkan/radv_meta_decompress.c | 2 +- src/amd/vulkan/radv_meta_fast_clear.c | 8 ++++---- src/amd/vulkan/radv_meta_resolve.c | 4 ++-- src/amd/vulkan/radv_private.h | 36 +++++++++++++++++++++++++++++++++++ 9 files changed, 72 insertions(+), 36 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7003818..e8a6d9b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -947,7 +947,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, va += image->offset + image->clear_value_offset; unsigned reg_offset = 0, reg_count = 0; - assert(image->surface.htile_size); + assert(radv_image_has_htile(image)); if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { ++reg_count; @@ -985,7 +985,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, va += image->offset + image->clear_value_offset; unsigned reg_offset = 0, reg_count = 0; - if (!image->surface.htile_size) + if (!radv_image_has_htile(image)) return; if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { @@ -1024,7 +1024,7 @@ radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->dcc_pred_offset; - assert(image->surface.dcc_size); + assert(radv_image_has_dcc(image)); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1045,7 +1045,7 @@ radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; - assert(image->cmask.size || image->surface.dcc_size); + assert(radv_image_has_cmask(image) || radv_image_has_dcc(image)); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1069,7 +1069,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; - if (!image->cmask.size && !image->surface.dcc_size) + if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image)) return; uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c; @@ -3631,7 +3631,7 @@ static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffe const VkImageSubresourceRange *range) { if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - if (image->fmask.size) + if (radv_image_has_fmask(image)) radv_initialise_cmask(cmd_buffer, image, 0xccccccccu); else radv_initialise_cmask(cmd_buffer, image, 0xffffffffu); @@ -3707,18 +3707,18 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index); unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index); - if (image->surface.htile_size) + if (radv_image_has_htile(image)) radv_handle_depth_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range, pending_clears); - if (image->cmask.size || image->fmask.size) + if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) radv_handle_cmask_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range); - if (image->surface.dcc_size) + if (radv_image_has_dcc(image)) radv_handle_dcc_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range); diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 41f8242..caf6f00 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3463,7 +3463,7 @@ radv_initialise_color_surface(struct radv_device *device, cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index); - if (iview->image->fmask.size) { + if (radv_image_has_fmask(iview->image)) { if (device->physical_device->rad_info.chip_class >= CIK) cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1); cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index); @@ -3498,7 +3498,7 @@ radv_initialise_color_surface(struct radv_device *device, S_028C74_NUM_FRAGMENTS(log_samples); } - if (iview->image->fmask.size) { + if (radv_image_has_fmask(iview->image)) { va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset; cb->cb_color_fmask = va >> 8; cb->cb_color_fmask |= iview->image->fmask.tile_swizzle; @@ -3548,7 +3548,7 @@ radv_initialise_color_surface(struct radv_device *device, format != V_028C70_COLOR_24_8) | S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian); - if ((iview->image->info.samples > 1) && iview->image->fmask.size) { + if ((iview->image->info.samples > 1) && radv_image_has_fmask(iview->image)) { cb->cb_color_info |= S_028C70_COMPRESSION(1); if (device->physical_device->rad_info.chip_class == SI) { unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height); @@ -3556,7 +3556,7 @@ radv_initialise_color_surface(struct radv_device *device, } } - if (iview->image->cmask.size && + if (radv_image_has_cmask(iview->image) && !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)) cb->cb_color_info |= S_028C70_FAST_CLEAR(1); @@ -3597,7 +3597,7 @@ radv_initialise_color_surface(struct radv_device *device, } /* This must be set for fast clear to work without FMASK. */ - if (!iview->image->fmask.size && + if (!radv_image_has_fmask(iview->image) && device->physical_device->rad_info.chip_class == SI) { unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index dd3189c..56b9ba1 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -299,7 +299,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class <= VI) meta_va += base_level_info->dcc_offset; } else if(!is_storage_image && image->tc_compatible_htile && - image->surface.htile_size) { + radv_image_has_htile(image)) { meta_va = gpu_address + image->htile_offset; } @@ -526,7 +526,7 @@ si_make_texture_descriptor(struct radv_device *device, } /* Initialize the sampler view for FMASK. */ - if (image->fmask.size) { + if (radv_image_has_fmask(image)) { uint32_t fmask_format, num_format; uint64_t gpu_address = radv_buffer_get_va(image->bo); uint64_t va; @@ -864,7 +864,7 @@ static inline bool radv_image_can_enable_dcc(struct radv_image *image) { return radv_image_can_enable_dcc_or_cmask(image) && - image->surface.dcc_size; + radv_image_has_dcc(image); } static inline bool @@ -1163,10 +1163,10 @@ bool radv_layout_has_htile(const struct radv_image *image, VkImageLayout layout, unsigned queue_mask) { - if (image->surface.htile_size && image->tc_compatible_htile) + if (radv_image_has_htile(image) && image->tc_compatible_htile) return layout != VK_IMAGE_LAYOUT_GENERAL; - return image->surface.htile_size && + return radv_image_has_htile(image) && (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL || layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) && queue_mask == (1u << RADV_QUEUE_GENERAL); @@ -1176,10 +1176,10 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image, VkImageLayout layout, unsigned queue_mask) { - if (image->surface.htile_size && image->tc_compatible_htile) + if (radv_image_has_htile(image) && image->tc_compatible_htile) return layout != VK_IMAGE_LAYOUT_GENERAL; - return image->surface.htile_size && + return radv_image_has_htile(image) && (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL || layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) && queue_mask == (1u << RADV_QUEUE_GENERAL); diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 7de2f2d..f78b956 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -558,7 +558,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, clear_value.depth != 1.0) || ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0))) return false; - if (iview->image->surface.htile_size && + if (radv_image_has_htile(iview->image) && iview->base_mip == 0 && iview->base_layer == 0 && radv_layout_is_htile_compressed(iview->image, layout, queue_mask) && @@ -682,7 +682,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer, VkImageAspectFlags aspects = clear_att->aspectMask; uint32_t clear_word, flush_bits; - if (!iview->image->surface.htile_size) + if (!radv_image_has_htile(iview->image)) return false; if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS) @@ -867,7 +867,7 @@ radv_get_cmask_fast_clear_value(const struct radv_image *image) /* The fast-clear value is different for images that have both DCC and * CMASK metadata. */ - if (image->surface.dcc_size) { + if (radv_image_has_dcc(image)) { /* DCC fast clear with MSAA should clear CMASK to 0xC. */ return image->info.samples > 1 ? 0xcccccccc : 0xffffffff; } @@ -989,7 +989,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, uint32_t cmask_clear_value; bool ret; - if (!iview->image->cmask.size && !iview->image->surface.dcc_size) + if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image)) return false; if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS) @@ -1030,7 +1030,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, goto fail; /* RB+ doesn't work with CMASK fast clear on Stoney. */ - if (!iview->image->surface.dcc_size && + if (!radv_image_has_dcc(iview->image) && cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) goto fail; @@ -1051,7 +1051,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image); /* clear cmask buffer */ - if (iview->image->surface.dcc_size) { + if (radv_image_has_dcc(iview->image)) { uint32_t reset_value; bool can_avoid_fast_clear_elim; vi_get_fast_clear_parameters(iview->image->vk_format, diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index a0ef18e..c8140b2 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -89,8 +89,8 @@ blit_surf_for_image_level_layer(struct radv_image *image, else if (subres->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) format = vk_format_stencil_only(format); - if (!image->surface.dcc_size && - !(image->surface.htile_size && image->tc_compatible_htile)) + if (!radv_image_has_dcc(image) && + !(radv_image_has_htile(image) && image->tc_compatible_htile)) format = vk_format_for_size(vk_format_get_blocksize(format)); return (struct radv_meta_blit2d_surf) { diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c index 7a56814..1a8058c 100644 --- a/src/amd/vulkan/radv_meta_decompress.c +++ b/src/amd/vulkan/radv_meta_decompress.c @@ -340,7 +340,7 @@ static void radv_process_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; VkPipeline pipeline_h; - if (!image->surface.htile_size) + if (!radv_image_has_htile(image)) return; radv_meta_save(&saved_state, cmd_buffer, diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index 928062b..327c1ae 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -593,15 +593,15 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_PASS); - if (decompress_dcc && image->surface.dcc_size) { + if (decompress_dcc && radv_image_has_dcc(image)) { pipeline = cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline; - } else if (image->fmask.size > 0) { + } else if (radv_image_has_fmask(image)) { pipeline = cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline; } else { pipeline = cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline; } - if (!decompress_dcc && image->surface.dcc_size) { + if (!decompress_dcc && radv_image_has_dcc(image)) { radv_emit_set_predication_state_from_image(cmd_buffer, image, true); cmd_buffer->state.predicating = true; } @@ -667,7 +667,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, &cmd_buffer->pool->alloc); } - if (image->surface.dcc_size) { + if (radv_image_has_dcc(image)) { cmd_buffer->state.predicating = false; radv_emit_set_predication_state_from_image(cmd_buffer, image, false); } diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 1973c55..bee3983 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -446,7 +446,7 @@ void radv_CmdResolveImage( if (src_image->info.array_size > 1) radv_finishme("vkCmdResolveImage: multisample array images"); - if (dest_image->surface.dcc_size) { + if (radv_image_has_dcc(dest_image)) { radv_initialize_dcc(cmd_buffer, dest_image, 0xffffffff); } unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format); @@ -648,7 +648,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image; - if (dst_img->surface.dcc_size) { + if (radv_image_has_dcc(dst_img)) { radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff); cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL; } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 9e655af..b4952b5 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1396,6 +1396,42 @@ radv_htile_enabled(const struct radv_image *image, unsigned level) return image->surface.htile_size && level == 0; } +/** + * Return whether the image has CMASK metadata for color surfaces. + */ +static inline bool +radv_image_has_cmask(const struct radv_image *image) +{ + return image->cmask.size; +} + +/** + * Return whether the image has FMASK metadata for color surfaces. + */ +static inline bool +radv_image_has_fmask(const struct radv_image *image) +{ + return image->fmask.size; +} + +/** + * Return whether the image has DCC metadata for color surfaces. + */ +static inline bool +radv_image_has_dcc(const struct radv_image *image) +{ + return image->surface.dcc_size; +} + +/** + * Return whether the image has HTILE metadata for depth surfaces. + */ +static inline bool +radv_image_has_htile(const struct radv_image *image) +{ + return image->surface.htile_size; +} + unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family); static inline uint32_t -- 2.7.4