From 0f983d69a43b71d62c407c51d154698bd41633b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 30 Mar 2018 19:28:37 +0000 Subject: [PATCH] [Hexagon] Avoid creating invalid offsets in packetizer Two memory instructions with a dependency only on the address register between the two (the first one of them being post-incrememnt) can be packetized together after the offset on the second was updated to the incremement value. Make sure that the new offset is valid for the instruction. llvm-svn: 328897 --- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 3 ++ .../CodeGen/Hexagon/packetize-update-offset.mir | 34 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 llvm/test/CodeGen/Hexagon/packetize-update-offset.mir diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 16d3733..135e90b 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -530,6 +530,9 @@ bool HexagonPacketizerList::updateOffset(SUnit *SUI, SUnit *SUJ) { return false; int64_t Offset = MI.getOperand(OPI).getImm(); + if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) + return false; + MI.getOperand(OPI).setImm(Offset + Incr); ChangedOffset = Offset; return true; diff --git a/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir new file mode 100644 index 0000000..9a142d0 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir @@ -0,0 +1,34 @@ +# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s + +# Make sure that we don't try to packetize the two stores together. The +# dependence on $r0 could be broken by updating the offset in the storeiri, +# but then the offset would become invalid for that instruction (it has to +# be a multiple of 4). + +# CHECK: S4_storeiri_io killed renamable $r0, 0, 0 + +--- | + define void @fred() { + ret void + } + + @g0 = global i8 zeroinitializer, align 2 + @g1 = global i32 zeroinitializer, align 4 +... + +--- +name: fred +tracksRegLiveness: true +body: | + bb.0: + successors: %bb.0, %bb.1 + liveins: $lc0, $r0, $r27 + $r1 = A2_addi $r0, 24 + $r0 = S2_storerb_pi $r0, 2, $r27 :: (store 1 into @g0, align 2) + S4_storeiri_io killed $r0, 0, 0 :: (store 4 into @g1, align 4) + $r0 = A2_tfr killed $r1 + ENDLOOP0 %bb.0, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0 + + bb.1: + +... -- 2.7.4