From 0f831aa805da1875aacdd205a4a0b0587e30df54 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 12 Jan 2023 11:01:54 +0100 Subject: [PATCH] GlobalISel: s/Op/Instr in some places. NFC This patch replaces `GMergeLikeOp` with `GMergeLikeInstr` and `MachineIRBuilder::buildAssertOp` with `buildAssertInstr` in order to remove ambiguity. Discussed in: https://reviews.llvm.org/D141372 --- llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h | 8 ++++---- .../llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h | 8 ++++---- llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 11 ++++++----- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 2 +- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index 58fe482..049efa6 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -153,7 +153,7 @@ public: /// Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES. /// All these have the common property of generating a single value from /// multiple sources. -class GMergeLikeOp : public GenericMachineInstr { +class GMergeLikeInstr : public GenericMachineInstr { public: /// Returns the number of source registers. unsigned getNumSources() const { return getNumOperands() - 1; } @@ -173,7 +173,7 @@ public: }; /// Represents a G_MERGE_VALUES. -class GMerge : public GMergeLikeOp { +class GMerge : public GMergeLikeInstr { public: static bool classof(const MachineInstr *MI) { return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES; @@ -181,7 +181,7 @@ public: }; /// Represents a G_CONCAT_VECTORS. -class GConcatVectors : public GMergeLikeOp { +class GConcatVectors : public GMergeLikeInstr { public: static bool classof(const MachineInstr *MI) { return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS; @@ -189,7 +189,7 @@ public: }; /// Represents a G_BUILD_VECTOR. -class GBuildVector : public GMergeLikeOp { +class GBuildVector : public GMergeLikeInstr { public: static bool classof(const MachineInstr *MI) { return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index 003af695..007a5935 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -826,7 +826,7 @@ public: // Check if sequence of elements from merge-like instruction is defined by // another sequence of elements defined by unmerge. Most often this is the // same sequence. Search for elements using findValueFromDefImpl. - bool isSequenceFromUnmerge(GMergeLikeOp &MI, unsigned MergeStartIdx, + bool isSequenceFromUnmerge(GMergeLikeInstr &MI, unsigned MergeStartIdx, GUnmerge *Unmerge, unsigned UnmergeIdxStart, unsigned NumElts, unsigned EltSize) { assert(MergeStartIdx + NumElts <= MI.getNumSources()); @@ -844,7 +844,7 @@ public: return true; } - bool tryCombineMergeLike(GMergeLikeOp &MI, + bool tryCombineMergeLike(GMergeLikeInstr &MI, SmallVectorImpl &DeadInsts, SmallVectorImpl &UpdatedDefs, GISelChangeObserver &Observer) { @@ -1162,7 +1162,7 @@ public: Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); MachineInstr *MergeI = MRI.getVRegDef(SrcReg); - if (!MergeI || !isa(MergeI)) + if (!MergeI || !isa(MergeI)) return false; Register DstReg = MI.getOperand(0).getReg(); @@ -1241,7 +1241,7 @@ public: break; } } - Changed = Finder.tryCombineMergeLike(cast(MI), DeadInsts, + Changed = Finder.tryCombineMergeLike(cast(MI), DeadInsts, UpdatedDefs, WrapperObserver); break; case TargetOpcode::G_EXTRACT: diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index b11ffcf..327b6a1 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -865,8 +865,8 @@ public: /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op, - unsigned Val) { + MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, + const SrcOp &Op, unsigned Val) { return buildInstr(Opc, Res, Op).addImm(Val); } @@ -875,7 +875,7 @@ public: /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size) { - return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size); + return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size); } /// Build and insert \p Res = G_ASSERT_SEXT Op, Size @@ -883,7 +883,7 @@ public: /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size) { - return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size); + return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size); } /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal @@ -891,7 +891,8 @@ public: /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal) { - return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value()); + return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op, + AlignVal.value()); } /// Build and insert `Res = G_LOAD Addr, MMO`. diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 01edd90..f93d1d0 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -1731,7 +1731,7 @@ bool CombinerHelper::matchCombineUnmergeMergeToPlainValues( auto &Unmerge = cast(MI); Register SrcReg = peekThroughBitcast(Unmerge.getSourceReg(), MRI); - auto *SrcInstr = getOpcodeDef(SrcReg, MRI); + auto *SrcInstr = getOpcodeDef(SrcReg, MRI); if (!SrcInstr) return false; -- 2.7.4