From 0f7a0a2865c6352780aa9d2472d9b126a4798bbe Mon Sep 17 00:00:00 2001 From: "zhiwei.yuan" Date: Fri, 15 Mar 2019 17:37:04 +0800 Subject: [PATCH] di: TL1 Scrolling subtiltes jitter seriously than p321 [1/1] PD#SWPL-3877 Problem: mcinfo canvas configuration is incorrect Solution: correct canvas config Verify: verified by t962x2_x301 Change-Id: I93958044faed25994d83a53948e226729357d2aa Signed-off-by: zhiwei.yuan --- drivers/amlogic/media/deinterlace/deinterlace.c | 9 +++++++-- drivers/amlogic/media/deinterlace/deinterlace_hw.c | 16 +++++++++++++--- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c index 9aa429d..ce72f8b 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.c +++ b/drivers/amlogic/media/deinterlace/deinterlace.c @@ -129,7 +129,7 @@ static di_dev_t *de_devp; static dev_t di_devno; static struct class *di_clsp; -static const char version_s[] = "2019-03-14b"; +static const char version_s[] = "2019-03-18a"; static int bypass_state = 1; static int bypass_all; @@ -2185,7 +2185,8 @@ static int di_init_buf(int width, int height, unsigned char prog_flag) mtn_size = (mtn_width * canvas_height)*4/16; count_size = (mtn_width * canvas_height)*4/16; mv_size = (mv_width * canvas_height)/5; - mc_size = canvas_height; + mc_size = roundup(canvas_height >> 1, canvas_align_width) << 1; + if (mc_mem_alloc) { di_buf_size = nr_size + mtn_size + count_size + mv_size + mc_size; @@ -2238,6 +2239,7 @@ static int di_init_buf(int width, int height, unsigned char prog_flag) di_buf->canvas_width[NR_CANVAS] = nr_canvas_width; di_buf->canvas_width[MTN_CANVAS] = mtn_canvas_width; di_buf->canvas_width[MV_CANVAS] = mv_canvas_width; + if (prog_flag) { di_buf->canvas_height = canvas_height; di_buf->nr_adr = de_devp->mem_start + @@ -2245,6 +2247,9 @@ static int di_init_buf(int width, int height, unsigned char prog_flag) di_buf->canvas_config_flag = 1; } else { di_buf->canvas_height = (canvas_height>>1); + di_buf->canvas_height = + roundup(di_buf->canvas_height, + canvas_align_width); di_buf->nr_adr = de_devp->mem_start + di_buf_size * i; di_buf->mtn_adr = de_devp->mem_start + diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 9c613aeb..5e5dd4c 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -330,6 +330,11 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned short *mcinfo_vadr) if (!lmv_lock_win_en) return; + if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) { + pr_debug("%s: only support G12A and after chips.\n", __func__); + return; + } + //tmp = di_vmap(mcinfo_adr, mcinfo_size, &bflg_vmap); if (mcinfo_vadr == NULL) { di_print("err:di_vmap failed\n"); @@ -339,11 +344,12 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned short *mcinfo_vadr) for (i = 0; i < (vf_height>>1); i++) { lmvs_init(&lines_mv[i], *(mcinfo_vadr+i)); j = i + (vf_height>>1); - lmvs_init(&lines_mv[j], *(mcinfo_vadr+i+272)); + /*288 = (canvas height(1088)/2 align to 64)*/ + lmvs_init(&lines_mv[j], *(mcinfo_vadr+i+288)); if (pr_mcinfo_cnt && j < (vf_height - 10) && j > (vf_height - offset_lmv)) { pr_info("MCINFO[%u]=0x%x\t", j, - *(mcinfo_vadr + i + 272)); + *(mcinfo_vadr + i + 288)); if (i%16 == 0) pr_info("\n"); } @@ -487,6 +493,10 @@ void di_hw_init(bool pd_enable, bool mc_enable) fifo_size_di = 0x120; } + /*enable lock win, suggestion from vlsi zheng.bao*/ + if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) + lmv_lock_win_en = 1; + DI_Wr(VD1_IF0_LUMA_FIFO_SIZE, fifo_size_vpp); DI_Wr(VD2_IF0_LUMA_FIFO_SIZE, fifo_size_vpp); /* 1a83 is vd2_if0_luma_fifo_size */ @@ -1322,7 +1332,7 @@ void enable_mc_di_pre_g12(struct DI_MC_MIF_s *mcinford_mif, RDMA_WR_BITS(MCINFRD_SCOPE_X, mcinford_mif->size_x, 16, 13); RDMA_WR_BITS(MCINFRD_SCOPE_Y, mcinford_mif->size_y, 16, 13); - RDMA_WR_BITS(MCINFRD_CTRL1, mcvecwr_mif->canvas_num, 16, 8); + RDMA_WR_BITS(MCINFRD_CTRL1, mcinford_mif->canvas_num, 16, 8); RDMA_WR_BITS(MCINFRD_CTRL1, 2, 0, 3); RDMA_WR_BITS(MCVECWR_X, mcvecwr_mif->size_x, 0, 13); -- 2.7.4