From 0f4c9c016caf52dc45934e0cbf82b1daabcf1d96 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 27 Mar 2023 09:20:07 -0700 Subject: [PATCH] [RISCV] Replace RISCV->RISC-V in strings. To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. D146449 already updated comments. Strings may have more user impact. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146451 --- clang/include/clang/Basic/AttrDocs.td | 2 +- clang/include/clang/Driver/Options.td | 2 +- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +- llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp | 2 +- .../Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp | 2 +- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 4 ++-- .../Target/RISCV/RISCVGatherScatterLowering.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp | 2 +- llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 2 +- llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp | 2 +- .../Target/RISCV/RISCVRedundantCopyElimination.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/test/CodeGen/RISCV/O0-pipeline.ll | 14 +++++------ llvm/test/CodeGen/RISCV/O3-pipeline.ll | 28 +++++++++++----------- llvm/utils/TableGen/CompressInstEmitter.cpp | 2 +- 20 files changed, 45 insertions(+), 45 deletions(-) diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 1bb9e69..02f0b6e 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2293,7 +2293,7 @@ as ``-mlong-calls`` and ``-mno-long-calls``. def RISCVInterruptDocs : Documentation { let Category = DocCatFunction; - let Heading = "interrupt (RISCV)"; + let Heading = "interrupt (RISC-V)"; let Content = [{ Clang supports the GNU style ``__attribute__((interrupt))`` attribute on RISCV targets. This attribute may be attached to a function definition and instructs diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 5d2089e..c01859b 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -185,7 +185,7 @@ def m_wasm_Features_Driver_Group : OptionGroup<"">, def m_x86_Features_Group : OptionGroup<"">, Group, Flags<[CoreOption]>, DocName<"X86">; def m_riscv_Features_Group : OptionGroup<"">, - Group, DocName<"RISCV">; + Group, DocName<"RISC-V">; def m_libc_Group : OptionGroup<"">, Group, Flags<[HelpHidden]>; diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 7789ef7..659f8e8 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -53,7 +53,7 @@ public: std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)) {} - StringRef getPassName() const override { return "RISCV Assembly Printer"; } + StringRef getPassName() const override { return "RISC-V Assembly Printer"; } bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp index c972859..2fcd9a4 100644 --- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp +++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-codegenprepare" -#define PASS_NAME "RISCV CodeGenPrepare" +#define PASS_NAME "RISC-V CodeGenPrepare" STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt"); diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp index 6a9b959..9cca526 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp @@ -24,7 +24,7 @@ using namespace llvm; #define RISCV_EXPAND_ATOMIC_PSEUDO_NAME \ - "RISCV atomic pseudo instruction expansion pass" + "RISC-V atomic pseudo instruction expansion pass" namespace { diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index b8e4665..d86ba82 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -23,8 +23,8 @@ using namespace llvm; -#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass" -#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass" +#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass" +#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass" namespace { diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp index 995647b..8a440ed 100644 --- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp @@ -59,7 +59,7 @@ public: } StringRef getPassName() const override { - return "RISCV gather/scatter lowering"; + return "RISC-V gather/scatter lowering"; } private: @@ -81,7 +81,7 @@ private: char RISCVGatherScatterLowering::ID = 0; INITIALIZE_PASS(RISCVGatherScatterLowering, DEBUG_TYPE, - "RISCV gather/scatter lowering pass", false, false) + "RISC-V gather/scatter lowering pass", false, false) FunctionPass *llvm::createRISCVGatherScatterLoweringPass() { return new RISCVGatherScatterLowering(); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index e44cf38..99f664b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-isel" -#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection" +#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection" namespace llvm::RISCV { #define GET_RISCVVSSEGTable_IMPL @@ -134,7 +134,7 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() { } if (Result) { - LLVM_DEBUG(dbgs() << "RISCV DAG preprocessing replacing:\nOld: "); + LLVM_DEBUG(dbgs() << "RISC-V DAG preprocessing replacing:\nOld: "); LLVM_DEBUG(N->dump(CurDAG)); LLVM_DEBUG(dbgs() << "\nNew: "); LLVM_DEBUG(Result->dump(CurDAG)); diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 3fa9fd6..b66ecc8 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -32,7 +32,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-insert-vsetvli" -#define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass" +#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass" static cl::opt DisableInsertVSETVLPHIOpt( "riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index faf47ed..77f63ee 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -951,7 +951,7 @@ unsigned RISCVInstrInfo::insertBranch( // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 0) && - "RISCV branch conditions have two components!"); + "RISC-V branch conditions have two components!"); // Unconditional branch. if (Cond.empty()) { diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp index 39d0a20..e6ae409 100644 --- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp +++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp @@ -75,7 +75,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-make-compressible" -#define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible" +#define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible" namespace { diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp index 55ded2c..a2b3065 100644 --- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp +++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp @@ -23,7 +23,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-merge-base-offset" -#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset" +#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset" namespace { class RISCVMergeBaseOffsetOpt : public MachineFunctionPass { diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp index a1de27f..fed3fa2 100644 --- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp +++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp @@ -39,7 +39,7 @@ using namespace llvm; #define DEBUG_TYPE "riscv-init-undef" -#define RISCV_INIT_UNDEF_NAME "RISCV init undef pass" +#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass" namespace { diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp index 92fba63..61d605f 100644 --- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp +++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp @@ -56,7 +56,7 @@ public: } StringRef getPassName() const override { - return "RISCV Redundant Copy Elimination"; + return "RISC-V Redundant Copy Elimination"; } private: @@ -68,7 +68,7 @@ private: char RISCVRedundantCopyElimination::ID = 0; INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim", - "RISCV redundant copy elimination pass", false, false) + "RISC-V Redundant Copy Elimination", false, false) static bool guaranteesZeroRegInBlock(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp index a26a3f2..173482e 100644 --- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp +++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp @@ -47,13 +47,13 @@ public: MachineFunctionPass::getAnalysisUsage(AU); } - StringRef getPassName() const override { return "RISCV sext.w Removal"; } + StringRef getPassName() const override { return "RISC-V sext.w Removal"; } }; } // end anonymous namespace char RISCVSExtWRemoval::ID = 0; -INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false, +INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISC-V sext.w Removal", false, false) FunctionPass *llvm::createRISCVSExtWRemovalPass() { diff --git a/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp b/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp index 8324f16..edf41b7 100644 --- a/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp +++ b/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp @@ -40,14 +40,14 @@ public: MachineFunctionPass::getAnalysisUsage(AU); } - StringRef getPassName() const override { return "RISCV Strip W Suffix"; } + StringRef getPassName() const override { return "RISC-V Strip W Suffix"; } }; } // end anonymous namespace char RISCVStripWSuffix::ID = 0; INITIALIZE_PASS(RISCVStripWSuffix, "riscv-strip-w-suffix", - "RISCV Strip W Suffix", false, false) + "RISC-V Strip W Suffix", false, false) FunctionPass *llvm::createRISCVStripWSuffixPass() { return new RISCVStripWSuffix(); diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 4b676f2..19b6b36 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -68,7 +68,7 @@ static cl::opt RVVVectorBitsMinOpt( static cl::opt EnableRISCVCopyPropagation( "riscv-enable-copy-propagation", - cl::desc("Enable the copy propagation with RISCV copy instr"), + cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden); extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index c87a0e3..f18e6a34 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -36,11 +36,11 @@ ; CHECK-NEXT: Insert stack protectors ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Assignment Tracking Analysis -; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection +; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Local Stack Slot Allocation -; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass -; CHECK-NEXT: RISCV Insert VSETVLI pass +; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Fast Register Allocator @@ -55,7 +55,7 @@ ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: Branch relaxation pass -; CHECK-NEXT: RISCV Make Compressible +; CHECK-NEXT: RISC-V Make Compressible ; CHECK-NEXT: Contiguously Lay Out Funclets ; CHECK-NEXT: StackMap Liveness Analysis ; CHECK-NEXT: Live DEBUG_VALUE analysis @@ -63,9 +63,9 @@ ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Stack Frame Layout Analysis -; CHECK-NEXT: RISCV pseudo instruction expansion pass -; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass +; CHECK-NEXT: RISC-V pseudo instruction expansion pass +; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter -; CHECK-NEXT: RISCV Assembly Printer +; CHECK-NEXT: RISC-V Assembly Printer ; CHECK-NEXT: Free MachineFunction diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 0ad0807..a010df1 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -28,8 +28,8 @@ ; CHECK-NEXT: Expand Atomic instructions ; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: RISCV gather/scatter lowering -; CHECK-NEXT: RISCV CodeGenPrepare +; CHECK-NEXT: RISC-V gather/scatter lowering +; CHECK-NEXT: RISC-V CodeGenPrepare ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Canonicalize natural loops @@ -79,7 +79,7 @@ ; CHECK-NEXT: Assignment Tracking Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis -; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection +; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Early Tail Duplication @@ -103,13 +103,13 @@ ; CHECK-NEXT: Machine Trace Metrics ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine InstCombiner -; RV64-NEXT: RISCV sext.w Removal -; RV64-NEXT: RISCV Strip W Suffix -; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass -; CHECK-NEXT: RISCV Merge Base Offset -; CHECK-NEXT: RISCV Insert VSETVLI pass +; RV64-NEXT: RISC-V sext.w Removal +; RV64-NEXT: RISC-V Strip W Suffix +; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass +; CHECK-NEXT: RISC-V Merge Base Offset +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Detect Dead Lanes -; CHECK-NEXT: RISCV init undef pass +; CHECK-NEXT: RISC-V init undef pass ; CHECK-NEXT: Process Implicit Definitions ; CHECK-NEXT: Remove unreachable machine basic blocks ; CHECK-NEXT: Live Variable Analysis @@ -136,7 +136,7 @@ ; CHECK-NEXT: Stack Slot Coloring ; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: Machine Loop Invariant Code Motion -; CHECK-NEXT: RISCV Redundant Copy Elimination +; CHECK-NEXT: RISC-V Redundant Copy Elimination ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Fixup Statepoint Caller Saved ; CHECK-NEXT: PostRA Machine Sink @@ -165,7 +165,7 @@ ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: Branch relaxation pass -; CHECK-NEXT: RISCV Make Compressible +; CHECK-NEXT: RISC-V Make Compressible ; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: Contiguously Lay Out Funclets ; CHECK-NEXT: StackMap Liveness Analysis @@ -176,9 +176,9 @@ ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Stack Frame Layout Analysis -; CHECK-NEXT: RISCV pseudo instruction expansion pass -; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass +; CHECK-NEXT: RISC-V pseudo instruction expansion pass +; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter -; CHECK-NEXT: RISCV Assembly Printer +; CHECK-NEXT: RISC-V Assembly Printer ; CHECK-NEXT: Free MachineFunction diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp index a7816c2..9d9b69f 100644 --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -904,4 +904,4 @@ void CompressInstEmitter::run(raw_ostream &o) { } static TableGen::Emitter::OptClass - X("gen-compress-inst-emitter", "Generate RISCV compressed instructions."); + X("gen-compress-inst-emitter", "Generate compressed instructions."); -- 2.7.4