From 0f23b763a96b06afffc6d2cbaaf1219a320af310 Mon Sep 17 00:00:00 2001
From: Andrew Trick <atrick@apple.com>
Date: Thu, 7 Mar 2013 19:21:08 +0000
Subject: [PATCH] pre-RA-sched debug-only fix

llvm-svn: 176638
---
 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index f843584..c009cfc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1360,8 +1360,10 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
     SmallVector<unsigned, 4> LRegs;
     if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
       break;
-    DEBUG(dbgs() << "    Interfering reg " << TRI->getName(LRegs[0])
-          << " SU #" << CurSU->NodeNum << '\n');
+    DEBUG(dbgs() << "    Interfering reg " <<
+          (LRegs[0] == TRI->getNumRegs() ? "CallResource"
+           : TRI->getName(LRegs[0]))
+           << " SU #" << CurSU->NodeNum << '\n');
     std::pair<LRegsMapT::iterator, bool> LRegsPair =
       LRegsMap.insert(std::make_pair(CurSU, LRegs));
     if (LRegsPair.second) {
-- 
2.7.4