From 0f149bf3dbce50b24e796838919dd1da9de4e260 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Tue, 28 Apr 2015 18:37:57 +0900 Subject: [PATCH] local/mmc: dw_mmc: exynos: Add SAMPLE_CLK_TUNING bit for eMMC SAMPLE_CLK_TUNING bits is used for sample clock fine grain adjustment. (Single stemp is approximately 200~500ps.) Signed-off-by: Jaehoon Chung --- drivers/mmc/host/dw_mmc-exynos.c | 3 ++- drivers/mmc/host/dw_mmc-exynos.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 7bf7054..6934b92 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -441,7 +441,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) clksel = mci_readl(host, CLKSEL); sample = (clksel + 1) & 0x7; - clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample) | + SDMMC_CLKSEL_SAMPLE_CLK_TUNING; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index 923aad5..c1f5d36 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -34,6 +34,7 @@ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z)) #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) +#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING BIT(6) #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) /* RCLK_EN register defines */ -- 2.7.4