From 0efdc7b31c2aeb3b0414a838e90014172b87302f Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 14 Jan 2021 12:55:19 +0100 Subject: [PATCH] i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [PR98670] I've made two mistakes in the *sse4_1_zero_extend* define_insn_and_split patterns. One is that when it uses vector_operand, it should use Bm rather than m constraint, and the other one is that because it is a post-reload splitter it needs isa attribute to select which alternatives are valid for which ISAs. Sorry for messing this up. 2021-01-14 Jakub Jelinek PR target/98670 * config/i386/sse.md (*sse4_1_zero_extendv8qiv8hi2_3, *sse4_1_zero_extendv4hiv4si2_3, *sse4_1_zero_extendv2siv2di2_3): Use Bm instead of m for non-avx. Add isa attribute. * gcc.target/i386/pr98670.c: New test. --- gcc/config/i386/sse.md | 15 +++++++++------ gcc/testsuite/gcc.target/i386/pr98670.c | 16 ++++++++++++++++ 2 files changed, 25 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr98670.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7f03fc4..42d4c44 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17721,7 +17721,7 @@ [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,v") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V16QI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -17745,7 +17745,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_expand "v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand") @@ -18031,7 +18032,7 @@ [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V8HI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -18053,7 +18054,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_insn "avx512f_v8qiv8di2" [(set (match_operand:V8DI 0 "register_operand" "=v") @@ -18447,7 +18449,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V4SI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -18467,7 +18469,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_expand "v2siv2di2" [(set (match_operand:V2DI 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr98670.c b/gcc/testsuite/gcc.target/i386/pr98670.c new file mode 100644 index 0000000..34a0095 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98670.c @@ -0,0 +1,16 @@ +/* PR target/98670 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include + +void foo (__m128i); +int a[6]; + +void +bar (void) +{ + __m128i d = *(__m128i *) (a + 2); + __m128i e = _mm_unpacklo_epi16 (d, (__m128i) {}); + foo (e); +} -- 2.7.4