From 0ec5f1e64fb2c38519bdefc85c018ed4f0a8d7c1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 9 Dec 2021 08:04:43 -0800 Subject: [PATCH] [RISCV] Reduce duplicate FP test cases. -Remove feq, fle, flt tests from *-arith.ll in favor of *-fcmp.ll which tests all predicates. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D113703 --- llvm/test/CodeGen/RISCV/double-arith.ll | 142 +--------------------- llvm/test/CodeGen/RISCV/float-arith.ll | 124 +------------------ llvm/test/CodeGen/RISCV/half-arith.ll | 208 +------------------------------- 3 files changed, 12 insertions(+), 462 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll index d3959af..e789b07 100644 --- a/llvm/test/CodeGen/RISCV/double-arith.ll +++ b/llvm/test/CodeGen/RISCV/double-arith.ll @@ -8,9 +8,10 @@ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; These tests are each targeted at a particular RISC-V FPU instruction. Most -; other files in this folder exercise LLVM IR instructions that don't directly -; match a RISC-V instruction. +; These tests are each targeted at a particular RISC-V FPU instruction. +; Compares and conversions can be found in double-fcmp.ll and double-convert.ll +; respectively. Some other double-*.ll files in this folder exercise LLVM IR +; instructions that don't directly match a RISC-V instruction. define double @fadd_d(double %a, double %b) nounwind { ; RV32IFD-LABEL: fadd_d: @@ -568,141 +569,6 @@ define double @fmax_d(double %a, double %b) nounwind { ret double %1 } -define i32 @feq_d(double %a, double %b) nounwind { -; RV32IFD-LABEL: feq_d: -; RV32IFD: # %bb.0: -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw a2, 8(sp) -; RV32IFD-NEXT: sw a3, 12(sp) -; RV32IFD-NEXT: fld ft0, 8(sp) -; RV32IFD-NEXT: sw a0, 8(sp) -; RV32IFD-NEXT: sw a1, 12(sp) -; RV32IFD-NEXT: fld ft1, 8(sp) -; RV32IFD-NEXT: feq.d a0, ft1, ft0 -; RV32IFD-NEXT: addi sp, sp, 16 -; RV32IFD-NEXT: ret -; -; RV64IFD-LABEL: feq_d: -; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fmv.d.x ft0, a1 -; RV64IFD-NEXT: fmv.d.x ft1, a0 -; RV64IFD-NEXT: feq.d a0, ft1, ft0 -; RV64IFD-NEXT: ret -; -; RV32I-LABEL: feq_d: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqdf2@plt -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: feq_d: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqdf2@plt -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp oeq double %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @flt_d(double %a, double %b) nounwind { -; RV32IFD-LABEL: flt_d: -; RV32IFD: # %bb.0: -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw a2, 8(sp) -; RV32IFD-NEXT: sw a3, 12(sp) -; RV32IFD-NEXT: fld ft0, 8(sp) -; RV32IFD-NEXT: sw a0, 8(sp) -; RV32IFD-NEXT: sw a1, 12(sp) -; RV32IFD-NEXT: fld ft1, 8(sp) -; RV32IFD-NEXT: flt.d a0, ft1, ft0 -; RV32IFD-NEXT: addi sp, sp, 16 -; RV32IFD-NEXT: ret -; -; RV64IFD-LABEL: flt_d: -; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fmv.d.x ft0, a1 -; RV64IFD-NEXT: fmv.d.x ft1, a0 -; RV64IFD-NEXT: flt.d a0, ft1, ft0 -; RV64IFD-NEXT: ret -; -; RV32I-LABEL: flt_d: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: flt_d: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt -; RV64I-NEXT: slti a0, a0, 0 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp olt double %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @fle_d(double %a, double %b) nounwind { -; RV32IFD-LABEL: fle_d: -; RV32IFD: # %bb.0: -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw a2, 8(sp) -; RV32IFD-NEXT: sw a3, 12(sp) -; RV32IFD-NEXT: fld ft0, 8(sp) -; RV32IFD-NEXT: sw a0, 8(sp) -; RV32IFD-NEXT: sw a1, 12(sp) -; RV32IFD-NEXT: fld ft1, 8(sp) -; RV32IFD-NEXT: fle.d a0, ft1, ft0 -; RV32IFD-NEXT: addi sp, sp, 16 -; RV32IFD-NEXT: ret -; -; RV64IFD-LABEL: fle_d: -; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fmv.d.x ft0, a1 -; RV64IFD-NEXT: fmv.d.x ft1, a0 -; RV64IFD-NEXT: fle.d a0, ft1, ft0 -; RV64IFD-NEXT: ret -; -; RV32I-LABEL: fle_d: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt -; RV32I-NEXT: slti a0, a0, 1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: fle_d: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt -; RV64I-NEXT: slti a0, a0, 1 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp ole double %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - declare double @llvm.fma.f64(double, double, double) define double @fmadd_d(double %a, double %b, double %c) nounwind { diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index 94a5ad7..3dd3a18 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -8,9 +8,10 @@ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; These tests are each targeted at a particular RISC-V FPU instruction. Most -; other files in this folder exercise LLVM IR instructions that don't directly -; match a RISC-V instruction. +; These tests are each targeted at a particular RISC-V FPU instruction. +; Compares and conversions can be found in float-fcmp.ll and float-convert.ll +; respectively. Some other float-*.ll files in this folder exercise LLVM IR +; instructions that don't directly match a RISC-V instruction. define float @fadd_s(float %a, float %b) nounwind { ; RV32IF-LABEL: fadd_s: @@ -495,123 +496,6 @@ define float @fmax_s(float %a, float %b) nounwind { ret float %1 } -define i32 @feq_s(float %a, float %b) nounwind { -; RV32IF-LABEL: feq_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a1 -; RV32IF-NEXT: fmv.w.x ft1, a0 -; RV32IF-NEXT: feq.s a0, ft1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: feq_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: feq.s a0, ft1, ft0 -; RV64IF-NEXT: ret -; -; RV32I-LABEL: feq_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqsf2@plt -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: feq_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqsf2@plt -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp oeq float %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @flt_s(float %a, float %b) nounwind { -; RV32IF-LABEL: flt_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a1 -; RV32IF-NEXT: fmv.w.x ft1, a0 -; RV32IF-NEXT: flt.s a0, ft1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: flt_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: flt.s a0, ft1, ft0 -; RV64IF-NEXT: ret -; -; RV32I-LABEL: flt_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: flt_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt -; RV64I-NEXT: slti a0, a0, 0 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp olt float %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @fle_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fle_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a1 -; RV32IF-NEXT: fmv.w.x ft1, a0 -; RV32IF-NEXT: fle.s a0, ft1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fle_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: fle.s a0, ft1, ft0 -; RV64IF-NEXT: ret -; -; RV32I-LABEL: fle_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt -; RV32I-NEXT: slti a0, a0, 1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: fle_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt -; RV64I-NEXT: slti a0, a0, 1 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret - %1 = fcmp ole float %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - declare float @llvm.fma.f32(float, float, float) define float @fmadd_s(float %a, float %b, float %c) nounwind { diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll index c8cfb45..154965c 100644 --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -8,9 +8,10 @@ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; These tests are each targeted at a particular RISC-V FPU instruction. Most -; other files in this folder exercise LLVM IR instructions that don't directly -; match a RISC-V instruction. +; These tests are each targeted at a particular RISC-V FPU instruction. +; Compares and conversions can be found in half-fcmp.ll and half-convert.ll +; respectively. Some other half-*.ll files in this folder exercise LLVM IR +; instructions that don't directly match a RISC-V instruction. define half @fadd_s(half %a, half %b) nounwind { ; RV32IZFH-LABEL: fadd_s: @@ -777,207 +778,6 @@ define half @fmax_s(half %a, half %b) nounwind { ret half %1 } -define i32 @feq_s(half %a, half %b) nounwind { -; RV32IZFH-LABEL: feq_s: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: feq.h a0, fa0, fa1 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: feq_s: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: feq.h a0, fa0, fa1 -; RV64IZFH-NEXT: ret -; -; RV32I-LABEL: feq_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s2, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s0, a1, -1 -; RV32I-NEXT: and a0, a0, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: and a0, s2, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __eqsf2@plt -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: feq_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill -; RV64I-NEXT: mv s2, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s0, a1, -1 -; RV64I-NEXT: and a0, a0, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: and a0, s2, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __eqsf2@plt -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 -; RV64I-NEXT: ret - %1 = fcmp oeq half %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @flt_s(half %a, half %b) nounwind { -; RV32IZFH-LABEL: flt_s: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: flt.h a0, fa0, fa1 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: flt_s: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: flt.h a0, fa0, fa1 -; RV64IZFH-NEXT: ret -; -; RV32I-LABEL: flt_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s2, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s0, a1, -1 -; RV32I-NEXT: and a0, a0, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: and a0, s2, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __ltsf2@plt -; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: flt_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill -; RV64I-NEXT: mv s2, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s0, a1, -1 -; RV64I-NEXT: and a0, a0, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: and a0, s2, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __ltsf2@plt -; RV64I-NEXT: slti a0, a0, 0 -; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 -; RV64I-NEXT: ret - %1 = fcmp olt half %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - -define i32 @fle_s(half %a, half %b) nounwind { -; RV32IZFH-LABEL: fle_s: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fle.h a0, fa0, fa1 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fle_s: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fle.h a0, fa0, fa1 -; RV64IZFH-NEXT: ret -; -; RV32I-LABEL: fle_s: -; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s2, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s0, a1, -1 -; RV32I-NEXT: and a0, a0, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: and a0, s2, s0 -; RV32I-NEXT: call __gnu_h2f_ieee@plt -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __lesf2@plt -; RV32I-NEXT: slti a0, a0, 1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret -; -; RV64I-LABEL: fle_s: -; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill -; RV64I-NEXT: mv s2, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s0, a1, -1 -; RV64I-NEXT: and a0, a0, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: and a0, s2, s0 -; RV64I-NEXT: call __gnu_h2f_ieee@plt -; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __lesf2@plt -; RV64I-NEXT: slti a0, a0, 1 -; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 -; RV64I-NEXT: ret - %1 = fcmp ole half %a, %b - %2 = zext i1 %1 to i32 - ret i32 %2 -} - declare half @llvm.fma.f16(half, half, half) define half @fmadd_s(half %a, half %b, half %c) nounwind { -- 2.7.4